From d2a9568c57f0aa02f097911d3811e002a1eec1b8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:59 +0000 Subject: mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- board/tqc/tqm85xx/sdram.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board/tqc/tqm85xx/sdram.c') diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index b2d3185..39a9e21 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -240,7 +240,7 @@ static phys_size_t sdram_setup(int casl) * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data * training */ - ddr->debug_3 |= 0x00000400; + ddr->debug[2] |= 0x00000400; /* * 5. Wait 200 micro-seconds @@ -282,18 +282,18 @@ static phys_size_t sdram_setup(int casl) /* * 8. Clear D3[21] to re-enable data training */ - ddr->debug_3 &= ~0x00000400; + ddr->debug[2] &= ~0x00000400; /* * 9. Set D2(21) to force data training to run */ - ddr->debug_2 |= 0x00000400; + ddr->debug[1] |= 0x00000400; /* * 10. Poll on D2[21] until it is cleared by hardware */ asm ("sync;isync;msync"); - while (ddr->debug_2 & 0x00000400) + while (ddr->debug[1] & 0x00000400) asm ("eieio"); /* -- cgit v1.1