From c00f69dbcd4a5e59d381274743b78e62485c5e4a Mon Sep 17 00:00:00 2001
From: Peter Korsgaard <peter.korsgaard@barco.com>
Date: Thu, 18 Oct 2012 01:21:12 +0000
Subject: am33xx: support board specific ddr settings

Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
---
 board/ti/am335x/board.c | 89 ++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 77 insertions(+), 12 deletions(-)

(limited to 'board/ti')

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 5279d1a..309a425 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -131,19 +131,79 @@ static void rtc32k_enable(void)
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
-#endif
 
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
-	/* The following boards are known to use DDR3. */
-	if (board_is_evm_sk() || board_is_bone_lt())
-		return EMIF_REG_SDRAM_TYPE_DDR3;
+static const struct ddr_data ddr2_data = {
+	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
 
-	return EMIF_REG_SDRAM_TYPE_DDR2;
-}
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+	.cmd0csratio = DDR2_RATIO,
+	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd0iclkout = DDR2_INVERT_CLKOUT,
+
+	.cmd1csratio = DDR2_RATIO,
+	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd1iclkout = DDR2_INVERT_CLKOUT,
+
+	.cmd2csratio = DDR2_RATIO,
+	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd2iclkout = DDR2_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+	.sdram_config = DDR2_EMIF_SDCFG,
+	.ref_ctrl = DDR2_EMIF_SDREF,
+	.sdram_tim1 = DDR2_EMIF_TIM1,
+	.sdram_tim2 = DDR2_EMIF_TIM2,
+	.sdram_tim3 = DDR2_EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = DDR3_RD_DQS,
+	.datawdsratio0 = DDR3_WR_DQS,
+	.datafwsratio0 = DDR3_PHY_FIFO_WE,
+	.datawrsratio0 = DDR3_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = DDR3_RATIO,
+	.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
+	.cmd0iclkout = DDR3_INVERT_CLKOUT,
+
+	.cmd1csratio = DDR3_RATIO,
+	.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
+	.cmd1iclkout = DDR3_INVERT_CLKOUT,
+
+	.cmd2csratio = DDR3_RATIO,
+	.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
+	.cmd2iclkout = DDR3_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = DDR3_EMIF_SDCFG,
+	.ref_ctrl = DDR3_EMIF_SDREF,
+	.sdram_tim1 = DDR3_EMIF_TIM1,
+	.sdram_tim2 = DDR3_EMIF_TIM2,
+	.sdram_tim3 = DDR3_EMIF_TIM3,
+	.zq_config = DDR3_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
+};
+#endif
 
 /*
  * early system init of muxing and clocks.
@@ -204,7 +264,12 @@ void s_init(void)
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 
-	config_ddr(board_memory_type());
+	if (board_is_evm_sk() || board_is_bone_lt())
+		config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data,
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+	else
+		config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
 #endif
 }
 
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