From 802bb57a584db2202a47d41ac730fe76ddeb4f33 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 Feb 2015 10:15:56 +0530 Subject: ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla --- board/ti/beagle_x15/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'board/ti') diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index db96e34..3a7e04d 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -47,7 +47,8 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, .sdram_config2 = 0x00000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, @@ -103,7 +104,8 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, .sdram_config2 = 0x00000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, -- cgit v1.1