From 3acb553439e3ee9f62f022f96f949c21811f8bdf Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Mar 2012 14:17:38 +0000 Subject: OMAP4460: TPS Ensure SET1 is selected after voltage configuration TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros Reported-by: Jerome Angeloni Signed-off-by: Nishanth Menon --- board/ti/panda/panda_mux_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/ti/panda/panda_mux_data.h') diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 5b66a14..3efc22a 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -76,7 +76,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ +{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ }; -- cgit v1.1