From 8626cb8021d92603cb6a305fb686510a8d14d6bd Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 8 Oct 2015 11:31:47 +0530 Subject: ARM: k2e/l: Apply WA for selecting PA clock source On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov " and based on the previous work done by "Hao Zhang " Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov Tested-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 859a260..bee42bc 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -81,6 +82,9 @@ int board_eth_init(bd_t *bis) if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; + if (cpu_is_k2e() || cpu_is_k2l()) + pll_pa_clk_sel(); + port_num = get_num_eth_ports(); for (j = 0; j < port_num; j++) { -- cgit v1.1 From 1985abe207c4f37357b44a79dcd481602d8f83d1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sat, 19 Sep 2015 15:00:23 +0530 Subject: ARM: keystone2: Use dtb images by default Now that OF_CONTROL is enabled on all keystone2 platforms, build the default images with DT. Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/README | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index b8d55e7..0fe5c3b 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -59,8 +59,8 @@ Supported boot modes: - UART boot Supported image formats: - - u-boot.bin: for loading and running u-boot.bin through Texas instruments - code composure studio (CCS) and for UART boot. + - u-boot-dtb.bin: for loading and running u-boot-dtb.bin through + Texas Instruments code composure studio (CCS) and for UART boot. - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - MLO: gpimage for programming AEMIF NAND flash for NAND boot @@ -69,18 +69,18 @@ Build instructions: Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. -To build u-boot.bin, u-boot-spi.gph, MLO: +To build u-boot-dtb.bin, u-boot-spi.gph, MLO: >make k2hk_evm_defconfig >make Load and Run U-Boot on keystone EVMs using CCS ========================================= -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot-dtb.bin on EVM. See instructions at below link for installing CCS on a Windows PC. http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading and running u-boot binary +Use u-boot-dtb.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup @@ -100,7 +100,7 @@ loading the u-boot binary on the target EVM. Instead do the following:- is connected: Unknown)" at the debug window (This is created once Target configuration is launched) and select "Connect Target". 2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot.bin + top level menu. At the Load Memory window, choose the file u-boot-dtb.bin through "Browse" button and click "next >" button. In the next window, enter Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" button. @@ -167,7 +167,7 @@ Load and Run U-Boot on keystone EVMs using UART download Open BMC and regular UART terminals. -1. On the regular UART port start xmodem transfer of the u-boot.bin +1. On the regular UART port start xmodem transfer of the u-boot-dtb.bin 2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM BMC> bootmode #4 MBC> reboot -- cgit v1.1 From f9c4a51c3e1bc73c5c2ae178cf41aa85bada1fc8 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sat, 19 Sep 2015 16:26:39 +0530 Subject: ARM: k2g: Add kconfig support Add Kconfig support Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 384b175..c0568ec 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -36,3 +36,16 @@ config SYS_CONFIG_NAME default "k2l_evm" endif + +if TARGET_K2G_EVM + +config SYS_BOARD + default "ks2_evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "k2g_evm" + +endif -- cgit v1.1 From bda920c65e7cc299e6ef0dc6e676fe672609ce12 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Sat, 19 Sep 2015 16:26:40 +0530 Subject: ARM: k2g: Add pll data Add pll data for k2g Signed-off-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/Makefile | 1 + board/ti/ks2_evm/board_k2g.c | 63 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 board/ti/ks2_evm/board_k2g.c (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 071dbee..b7c5402 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_K2G_EVM) += board_k2g.o diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c new file mode 100644 index 0000000..6234baa --- /dev/null +++ b/board/ti/ks2_evm/board_k2g.c @@ -0,0 +1,63 @@ +/* + * K2G EVM : Board initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; +static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; +static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; +static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; +static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10}; + +struct pll_init_data *get_pll_init_data(int pll) +{ + struct pll_init_data *data = NULL; + + switch (pll) { + case MAIN_PLL: + data = &main_pll_config; + break; + case TETRIS_PLL: + data = &tetris_pll_config[speed]; + break; + case NSS_PLL: + data = &nss_pll_config; + break; + case UART_PLL: + data = &uart_pll_config; + break; + case DDR3_PLL: + data = &ddr_pll_config; + break; + default: + data = NULL; + } + + return data; +} + +s16 divn_val[16] = { + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_init_keystone_plls(void) +{ + init_plls(); +} +#endif -- cgit v1.1 From e6d71e1ca5dc40e871e53ad0d14d68676cf92601 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Sat, 19 Sep 2015 16:26:41 +0530 Subject: ARM: k2g: Add clock information Add clock information for Galileo Signed-off-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla Signed-off-by: Mugunthan V N --- board/ti/ks2_evm/board_k2g.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 6234baa..2d4602f 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -9,6 +9,16 @@ #include #include +#define SYS_CLK 24000000 + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = SYS_CLK, + [pa_clk] = SYS_CLK, + [tetris_clk] = SYS_CLK, + [ddr3a_clk] = SYS_CLK, + [uart_clk] = SYS_CLK, +}; + static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; -- cgit v1.1 From 235dd6e8d1696f85e6ff536bd64bf1e4240ae368 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Sat, 19 Sep 2015 16:26:43 +0530 Subject: ARM: k2g: Add ddr3 info Add ddr3 related info Signed-off-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/Makefile | 1 + board/ti/ks2_evm/board.c | 3 ++- board/ti/ks2_evm/board_k2g.c | 6 ++--- board/ti/ks2_evm/ddr3_k2g.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 4 deletions(-) create mode 100644 board/ti/ks2_evm/ddr3_k2g.c (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index b7c5402..d60496e 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o obj-$(CONFIG_K2G_EVM) += board_k2g.o +obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index bee42bc..7a5509a 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -43,7 +43,8 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); + if (ddr3_size) + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; } diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 2d4602f..81cef70 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -23,7 +23,7 @@ static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; struct pll_init_data *get_pll_init_data(int pll) { @@ -34,7 +34,7 @@ struct pll_init_data *get_pll_init_data(int pll) data = &main_pll_config; break; case TETRIS_PLL: - data = &tetris_pll_config[speed]; + data = &tetris_pll_config; break; case NSS_PLL: data = &nss_pll_config; @@ -43,7 +43,7 @@ struct pll_init_data *get_pll_init_data(int pll) data = &uart_pll_config; break; case DDR3_PLL: - data = &ddr_pll_config; + data = &ddr3_pll_config; break; default: data = NULL; diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c new file mode 100644 index 0000000..344961d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -0,0 +1,64 @@ +/* + * K2G: DDR3 initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +struct ddr3_phy_config ddr3phy_800_2g = { + .pllcr = 0x000DC000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, + .ptr3 = 0x06C30D40ul, + .ptr4 = 0x06413880ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x550F6644ul, + .dtpr1 = 0x328341E0ul, + .dtpr2 = 0x50022A00ul, + .mr0 = 0x00001430ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F03D09ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x00000F81ul, +}; + +struct ddr3_emif_config ddr3_800_2g = { + .sdcfg = 0x62005662ul, + .sdtim1 = 0x0A385033ul, + .sdtim2 = 0x00001CA5ul, + .sdtim3 = 0x21ADFF32ul, + .sdtim4 = 0x533F067Ful, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00000C34ul, +}; + +u32 ddr3_init(void) +{ + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); + + return 0; +} + +inline int ddr3_get_size(void) +{ + return 2; +} -- cgit v1.1 From dd78b8cf30fe6d12f6af1d66ce7551c44fe21250 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Sat, 19 Sep 2015 16:26:45 +0530 Subject: ARM: k2g: Add pin mux data Add pin mux data for k2g-evm Signed-off-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board_k2g.c | 3 + board/ti/ks2_evm/mux-k2g.h | 313 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 316 insertions(+) create mode 100644 board/ti/ks2_evm/mux-k2g.h (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 81cef70..3852138 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -8,6 +8,7 @@ */ #include #include +#include "mux-k2g.h" #define SYS_CLK 24000000 @@ -61,6 +62,8 @@ int board_early_init_f(void) { init_plls(); + k2g_mux_config(); + return 0; } #endif diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h new file mode 100644 index 0000000..773f9b7 --- /dev/null +++ b/board/ti/ks2_evm/mux-k2g.h @@ -0,0 +1,313 @@ +/* + * K2G EVM: Pinmux configuration + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +struct pin_cfg k2g_evm_pin_cfg[] = { + /* GPMC */ + { 0, MODE(0) }, /* GPMCAD0 */ + { 1, MODE(0) }, /* GPMCAD1 */ + { 2, MODE(0) }, /* GPMCAD2 */ + { 3, MODE(0) }, /* GPMCAD3 */ + { 4, MODE(0) }, /* GPMCAD4 */ + { 5, MODE(0) }, /* GPMCAD5 */ + { 6, MODE(0) }, /* GPMCAD6 */ + { 7, MODE(0) }, /* GPMCAD7 */ + { 8, MODE(0) }, /* GPMCAD8 */ + { 9, MODE(0) }, /* GPMCAD9 */ + { 10, MODE(0) }, /* GPMCAD10 */ + { 11, MODE(0) }, /* GPMCAD11 */ + { 12, MODE(0) }, /* GPMCAD12 */ + { 13, MODE(0) }, /* GPMCAD13 */ + { 14, MODE(0) }, /* GPMCAD14 */ + { 15, MODE(0) }, /* GPMCAD15 */ + { 17, MODE(0) }, /* GPMCADVNALE */ + { 18, MODE(0) }, /* GPMCOENREN */ + { 19, MODE(0) }, /* GPMCWEN */ + { 20, MODE(0) }, /* GPMCBE0NCLE */ + { 22, MODE(0) }, /* GPMCWAIT0 */ + { 24, MODE(0) }, /* GPMCWPN */ + { 26, MODE(0) }, /* GPMCCSN0 */ + + /* GPIOs */ + { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */ + { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */ + { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */ + { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */ + { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */ + { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */ + { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */ + { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */ + { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */ + { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */ + { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */ + { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */ + { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/ + { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */ + { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */ + { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */ + { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */ + { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */ + + /* MLB */ + { 23, MODE(2) }, /* SOC_MLBCLK */ + { 25, MODE(2) }, /* SOC_MLBSIG */ + { 27, MODE(2) }, /* SOC_MLBDAT */ + + /* DSS */ + { 30, MODE(0) }, /* SOC_DSSDATA23 */ + { 31, MODE(0) }, /* SOC_DSSDATA22 */ + { 32, MODE(0) }, /* SOC_DSSDATA21 */ + { 33, MODE(0) }, /* SOC_DSSDATA20 */ + { 34, MODE(0) }, /* SOC_DSSDATA19 */ + { 35, MODE(0) }, /* SOC_DSSDATA18 */ + { 36, MODE(0) }, /* SOC_DSSDATA17 */ + { 37, MODE(0) }, /* SOC_DSSDATA16 */ + { 38, MODE(0) }, /* SOC_DSSDATA15 */ + { 39, MODE(0) }, /* SOC_DSSDATA14 */ + { 40, MODE(0) }, /* SOC_DSSDATA13 */ + { 41, MODE(0) }, /* SOC_DSSDATA12 */ + { 42, MODE(0) }, /* SOC_DSSDATA11 */ + { 43, MODE(0) }, /* SOC_DSSDATA10 */ + { 44, MODE(0) }, /* SOC_DSSDATA9 */ + { 45, MODE(0) }, /* SOC_DSSDATA8 */ + { 46, MODE(0) }, /* SOC_DSSDATA7 */ + { 47, MODE(0) }, /* SOC_DSSDATA6 */ + { 48, MODE(0) }, /* SOC_DSSDATA5 */ + { 49, MODE(0) }, /* SOC_DSSDATA4 */ + { 50, MODE(0) }, /* SOC_DSSDATA3 */ + { 51, MODE(0) }, /* SOC_DSSDATA2 */ + { 52, MODE(0) }, /* SOC_DSSDATA1 */ + { 53, MODE(0) }, /* SOC_DSSDATA0 */ + { 54, MODE(0) }, /* SOC_DSSVSYNC */ + { 55, MODE(0) }, /* SOC_DSSHSYNC */ + { 56, MODE(0) }, /* SOC_DSSPCLK */ + { 57, MODE(0) }, /* SOC_DSS_DE */ + { 58, MODE(0) }, /* SOC_DSS_FID */ + { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */ + + /* MMC1 */ + { 59, MODE(0) }, /* SOC_MMC1_DAT7 */ + { 60, MODE(0) }, /* SOC_MMC1_DAT6 */ + { 61, MODE(0) }, /* SOC_MMC1_DAT5 */ + { 62, MODE(0) }, /* SOC_MMC1_DAT4 */ + { 63, MODE(0) }, /* SOC_MMC1_DAT3 */ + { 64, MODE(0) }, /* SOC_MMC1_DAT2 */ + { 65, MODE(0) }, /* SOC_MMC1_DAT1 */ + { 66, MODE(0) }, /* SOC_MMC1_DAT0 */ + { 67, MODE(0) }, /* SOC_MMC1_CLK */ + { 68, MODE(0) }, /* SOC_MMC1_CMD */ + { 69, MODE(0) }, /* MMC1SDCD TP125 */ + { 70, MODE(0) }, /* SOC_MMC1_SDWP */ + { 71, MODE(0) }, /* MMC1POW TP124 */ + + /* RGMII */ + { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ + { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ + { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ + { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ + { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ + { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ + { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ + { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ + { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ + { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ + { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ + { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ + { 98, MODE(0) }, /* SOC_MDIO_DATA */ + { 99, MODE(0) }, /* SOC_MDIO_CLK */ + + /* PWM */ + { 73, MODE(4) }, /* SOC_EHRPWM3A */ + { 74, MODE(4) }, /* SOC_EHRPWM3B */ + { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */ + { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */ + { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */ + { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */ + { 199, MODE(4) }, /* SOC_EHRPWM4A */ + { 200, MODE(4) }, /* SOC_EHRPWM4B */ + { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */ + { 219, MODE(4) }, /* SOC_EHRPWM5A */ + { 220, MODE(4) }, /* SOC_EHRPWM5B */ + { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */ + + /* SPI3 */ + { 86, MODE(1) }, /* SOC_SPI3_SCS0 */ + { 88, MODE(1) }, /* SOC_SPI3_CLK */ + { 89, MODE(1) }, /* SOC_SPI3_MISO */ + { 90, MODE(1) }, /* SOC_SPI3_MOSI */ + + /* CLK */ + { 97, MODE(0) }, /* SMD - TP132 */ + + /* SPI0 */ + { 100, MODE(0) }, /* SOC_SPI0_SCS0 */ + { 101, MODE(0) }, /* SOC_SPI0_SCS1 */ + { 102, MODE(0) }, /* SOC_SPI0_CLK */ + { 103, MODE(0) }, /* SOC_SPI0_MISO */ + { 104, MODE(0) }, /* SOC_SPI0_MOSI */ + + /* SPI1 NORFLASH */ + { 105, MODE(0) }, /* SOC_SPI1_SCS0 */ + { 107, MODE(0) }, /* SOC_SPI1_CLK */ + { 108, MODE(0) }, /* SOC_SPI1_MISO */ + { 109, MODE(0) }, /* SOC_SPI1_MOSI */ + + /* SPI2 */ + { 110, MODE(0) }, /* SOC_SPI2_SCS0 */ + { 111, MODE(1) }, /* SOC_HOUT */ + { 112, MODE(0) }, /* SOC_SPI2_CLK */ + { 113, MODE(0) }, /* SOC_SPI2_MISO */ + { 114, MODE(0) }, /* SOC_SPI2_MOSI */ + + /* UART0 */ + { 115, MODE(0) }, /* SOC_UART0_RXD */ + { 116, MODE(0) }, /* SOC_UART0_TXD */ + { 117, MODE(0) }, /* SOC_UART0_CTSn */ + { 118, MODE(0) }, /* SOC_UART0_RTSn */ + + /* UART1 */ + { 119, MODE(0) }, /* SOC_UART1_RXD */ + { 120, MODE(0) }, /* SOC_UART1_TXD */ + { 121, MODE(0) }, /* SOC_UART1_CTSn */ + { 122, MODE(0) }, /* SOC_UART1_RTSn */ + + /* UART2 */ + { 123, MODE(0) }, /* SOC_UART2_RXD */ + { 124, MODE(0) }, /* SOC_UART2_TXD */ + { 125, MODE(0) }, /* UART0_TXVR_EN */ + { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */ + + /* DCAN */ + { 127, MODE(0) }, /* SOC_DCAN0_TX */ + { 128, MODE(0) }, /* SOC_DCAN0_RX */ + { 137, MODE(1) }, /* SOC_DCAN1_TX */ + { 138, MODE(1) }, /* SOC_DCAN1_RX */ + + /* QSPI */ + { 129, MODE(0) }, /* SOC_QSPI_CLK */ + { 130, MODE(0) }, /* SOC_QSPI_RTCLK */ + { 131, MODE(0) }, /* SOC_QSPI_D0 */ + { 132, MODE(0) }, /* SOC_QSPI_D1 */ + { 133, MODE(0) }, /* SOC_QSPI_D2 */ + { 134, MODE(0) }, /* SOC_QSPI_D3 */ + { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ + { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */ + + /* MCASP2 */ + { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */ + { 140, MODE(4) }, /* SOC_MCASP2AXR1 */ + { 141, MODE(4) }, /* SOC_MCASP2AXR2 */ + { 142, MODE(4) }, /* SOC_MCASP2AXR3 */ + { 143, MODE(4) }, /* SOC_MCASP2AXR4 */ + { 144, MODE(4) }, /* SOC_MCASP2AXR5 */ + { 145, MODE(4) }, /* SOC_McASP2ACLKR */ + { 146, MODE(4) }, /* SOC_McASP2FSR */ + { 147, MODE(4) }, /* SOC_McASP2AHCLKR */ + { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */ + { 149, MODE(4) }, /* SOC_McASP2FSX */ + { 150, MODE(4) }, /* SOC_McASP2AHCLKX */ + { 151, MODE(4) }, /* SOC_McASP2ACLKX */ + + /* MCASP1 */ + { 152, MODE(4) }, /* SOC_MCASP1ACLKR */ + { 153, MODE(4) }, /* SOC_MCASP1FSR */ + { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */ + { 155, MODE(4) }, /* SOC_MCASP1ACLKX */ + { 156, MODE(4) }, /* SOC_MCASP1FSX */ + { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */ + { 158, MODE(4) }, /* SOC_MCASP1AMUTE */ + { 159, MODE(4) }, /* SOC_MCASP1AXR0 */ + { 160, MODE(4) }, /* SOC_MCASP1AXR1 */ + { 161, MODE(4) }, /* SOC_MCASP1AXR2 */ + { 162, MODE(4) }, /* SOC_MCASP1AXR3 */ + { 163, MODE(4) }, /* SOC_MCASP1AXR4 */ + { 164, MODE(4) }, /* SOC_MCASP1AXR5 */ + { 165, MODE(4) }, /* SOC_MCASP1AXR6 */ + { 166, MODE(4) }, /* SOC_MCASP1AXR7 */ + { 167, MODE(4) }, /* SOC_MCASP1AXR8 */ + { 168, MODE(4) }, /* SOC_MCASP1AXR9 */ + + /* MCASP0 */ + { 169, MODE(4) }, /* SOC_MCASP0AMUTE */ + { 170, MODE(4) }, /* SOC_MCASP0ACLKR */ + { 171, MODE(4) }, /* SOC_MCASP0FSR */ + { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */ + { 173, MODE(4) }, /* SOC_MCASP0ACLKX */ + { 174, MODE(4) }, /* SOC_MCASP0FSX */ + { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */ + { 176, MODE(4) }, /* SOC_MCASP0AXR0 */ + { 177, MODE(4) }, /* SOC_MCASP0AXR1 */ + { 178, MODE(4) }, /* SOC_MCASP0AXR2 */ + { 179, MODE(4) }, /* SOC_MCASP0AXR3 */ + { 180, MODE(4) }, /* SOC_MCASP0AXR4 */ + { 181, MODE(4) }, /* SOC_MCASP0AXR5 */ + { 182, MODE(4) }, /* SOC_MCASP0AXR6 */ + { 183, MODE(4) }, /* SOC_MCASP0AXR7 */ + { 184, MODE(4) }, /* SOC_MCASP0AXR8 */ + { 185, MODE(4) }, /* SOC_MCASP0AXR9 */ + { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */ + { 188, MODE(4) }, /* SOC_MCASP0AXR12 */ + { 189, MODE(4) }, /* SOC_MCASP0AXR13 */ + { 190, MODE(4) }, /* SOC_MCASP0AXR14 */ + { 191, MODE(4) }, /* SOC_MCASP0AXR15 */ + + /* MMC0 */ + { 192, MODE(2) }, /* SOC_MMC0_DAT3 */ + { 193, MODE(2) }, /* SOC_MMC0_DAT2 */ + { 194, MODE(2) }, /* SOC_MMC0_DAT1 */ + { 195, MODE(2) }, /* SOC_MMC0_DAT0 */ + { 196, MODE(2) }, /* SOC_MMC0_CLK */ + { 197, MODE(2) }, /* SOC_MMC0_CMD */ + { 187, MODE(2) }, /* SOC_MMC0_SDCD */ + + /* McBSP */ + { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */ + { 29, MODE(2) }, /* SOC_TIMO1 */ + { 210, MODE(2) }, /* SOC_MCBSPDR */ + { 211, MODE(2) }, /* SOC_MCBSPDX */ + { 212, MODE(2) }, /* SOC_MCBSPFSX */ + { 213, MODE(2) }, /* SOC_MCBSPCLKX */ + { 214, MODE(2) }, /* SOC_MCBSPFSR */ + { 215, MODE(2) }, /* SOC_MCBSPCLKR */ + + /* I2C */ + { 223, MODE(0) }, /* SOC_I2C0_SCL */ + { 224, MODE(0) }, /* SOC_I2C0_SDA */ + { 225, MODE(0) }, /* SOC_I2C1_SCL */ + { 226, MODE(0) }, /* SOC_I2C1_SDA */ + { 227, MODE(0) }, /* SOC_I2C2_SCL */ + { 228, MODE(0) }, /* SOC_I2C2_SDA */ + { 229, MODE(0) }, /* NMIz */ + { 230, MODE(0) }, /* LRESETz */ + { 231, MODE(0) }, /* LRESETNMIENz */ + + { 235, MODE(0) }, + { 236, MODE(0) }, + { 237, MODE(0) }, + { 238, MODE(0) }, + { 239, MODE(0) }, + { 240, MODE(0) }, + { 241, MODE(0) }, + { 242, MODE(0) }, + { 243, MODE(0) }, + { 244, MODE(0) }, + + { 258, MODE(0) }, /* USB0DRVVBUS */ + { 259, MODE(0) }, /* USB1DRVVBUS */ + { MAX_PIN_N, } +}; + +void k2g_mux_config(void) +{ + configure_pin_mux(k2g_evm_pin_cfg); +} -- cgit v1.1 From bf7bd4e725105fc0f6f43df6d01d85c6df3ce4eb Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Sat, 19 Sep 2015 16:26:48 +0530 Subject: driver: net: keystone_net: fix phy mode configuration Phy mode is a board property and it can be different between multiple board and ports, so it should not be hardcoded in driver to one specific mode. So adding a field in eth_priv_t structure to pass phy mode to driver. Signed-off-by: Mugunthan V N Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board_k2e.c | 8 ++++++++ board/ti/ks2_evm/board_k2hk.c | 4 ++++ board/ti/ks2_evm/board_k2l.c | 4 ++++ 3 files changed, 16 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index dc00cf6..f58f623 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -82,6 +82,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC1", @@ -89,6 +90,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC2", @@ -96,6 +98,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC3", @@ -103,6 +106,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC4", @@ -110,6 +114,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 4, .slave_port = 5, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC5", @@ -117,6 +122,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 5, .slave_port = 6, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC6", @@ -124,6 +130,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 6, .slave_port = 7, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC7", @@ -131,6 +138,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 7, .slave_port = 8, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 6e681d7..0bd6b86 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -76,6 +76,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC1", @@ -83,6 +84,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC2", @@ -90,6 +92,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC3", @@ -97,6 +100,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index f35a64f..d750ad3 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -75,6 +75,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC1", @@ -82,6 +83,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC2", @@ -89,6 +91,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC3", @@ -96,6 +99,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; -- cgit v1.1 From 91266ccbb2aaef87f6ff10292470abd65fa9c3ad Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Sat, 19 Sep 2015 16:26:52 +0530 Subject: ARM: k2g: Add Ethernet Support Add Ethernet support for tftp support Signed-off-by: Vitaly Andrianov Signed-off-by: Mugunthan V N Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board.c | 5 +++++ board/ti/ks2_evm/board_k2g.c | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 7a5509a..73d94a6 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -75,9 +75,14 @@ int board_eth_init(bd_t *bis) int port_num; char link_type_name[32]; + if (cpu_is_k2g()) + writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); + /* By default, select PA PLL clock as PA clock source */ +#ifndef CONFIG_SOC_K2G if (psc_enable_module(KS2_LPSC_PA)) return -1; +#endif if (psc_enable_module(KS2_LPSC_CPGMAC)) return -1; if (psc_enable_module(KS2_LPSC_CRYPTO)) diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 3852138..b2bc793 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -8,6 +8,7 @@ */ #include #include +#include #include "mux-k2g.h" #define SYS_CLK 24000000 @@ -74,3 +75,21 @@ void spl_init_keystone_plls(void) init_plls(); } #endif + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2G_EMAC", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif -- cgit v1.1 From 3b68939fa0b4191028e4cc5817b59219fd4baecd Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Sat, 19 Sep 2015 16:26:53 +0530 Subject: ARM: k2g: add SD card and eMMC support Add MMC support for k2g Signed-off-by: Roger Quadros Signed-off-by: Lokesh Vutla Tested-by: Mugunthan V N --- board/ti/ks2_evm/board_k2g.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index b2bc793..3e1dd4c 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include "mux-k2g.h" #define SYS_CLK 24000000 @@ -58,6 +60,20 @@ s16 divn_val[16] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + if (psc_enable_module(KS2_LPSC_MMC)) { + printf("%s module enabled failed\n", __func__); + return -1; + } + + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -- cgit v1.1 From 83b9bf11feb1a88588eaf7f89c763bc59a7010d1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sat, 19 Sep 2015 16:26:54 +0530 Subject: ARM: k2g: Enable SPI flash GPIO1_9 controls SPI flash on k2g evm. So make GPIO1_9 as output pin, inorder to use SPI. Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board_k2g.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 3e1dd4c..cdeb056 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -81,6 +81,12 @@ int board_early_init_f(void) k2g_mux_config(); + /* deassert FLASH_HOLD */ + clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, + BIT(9)); + setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(9)); + return 0; } #endif -- cgit v1.1 From b9ca4ab45392b7fac1538506b112454a603922ce Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sat, 19 Sep 2015 16:26:56 +0530 Subject: ARM: k2g: Add config file Add config file for k2g Signed-off-by: Lokesh Vutla Signed-off-by: Mugunthan V N Signed-off-by: Vitaly Andrianov --- board/ti/ks2_evm/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS index 87c36c9..999ef0a 100644 --- a/board/ti/ks2_evm/MAINTAINERS +++ b/board/ti/ks2_evm/MAINTAINERS @@ -8,3 +8,5 @@ F: include/configs/k2e_evm.h F: configs/k2e_evm_defconfig F: include/configs/k2l_evm.h F: configs/k2l_evm_defconfig +F: include/configs/k2g_evm.h +F: configs/k2g_evm_defconfig -- cgit v1.1