From 527b9f7ad8da4222a53b826479b808a0f105988f Mon Sep 17 00:00:00 2001
From: Winter Wang <wente.wang@nxp.com>
Date: Thu, 13 Oct 2016 12:57:20 +0800
Subject: MA-8840 picosom: change to 512M ddr ram

Pin GPIO5_IO01 is for detect 256M/512M version,
this pin is pulled high for 512M version and low
for 256M version.
Just print version check message out .

Signed-off-by: Winter Wang <wente.wang@nxp.com>
---
 board/technexion/picosom-imx6ul/imximage.cfg     | 10 ++++-----
 board/technexion/picosom-imx6ul/picosom-imx6ul.c | 26 +++++++++++++++++++++++-
 2 files changed, 30 insertions(+), 6 deletions(-)

(limited to 'board/technexion')

diff --git a/board/technexion/picosom-imx6ul/imximage.cfg b/board/technexion/picosom-imx6ul/imximage.cfg
index 9a7db2f..8283673 100644
--- a/board/technexion/picosom-imx6ul/imximage.cfg
+++ b/board/technexion/picosom-imx6ul/imximage.cfg
@@ -81,9 +81,9 @@ DATA 4 0x020E0248 0x00000030
 DATA 4 0x021B001C 0x00008000
 DATA 4 0x021B0800 0xA1390003
 DATA 4 0x021B080C 0x00000000
-DATA 4 0x021B083C 0x01380134
-DATA 4 0x021B0848 0x40404244
-DATA 4 0x021B0850 0x40405050
+DATA 4 0x021B083C 0x41490145
+DATA 4 0x021B0848 0x40404546
+DATA 4 0x021B0850 0x4040524D
 DATA 4 0x021B081C 0x33333333
 DATA 4 0x021B0820 0x33333333
 DATA 4 0x021B082C 0xf3333333
@@ -99,8 +99,8 @@ DATA 4 0x021B0018 0x00201740
 DATA 4 0x021B001C 0x00008000
 DATA 4 0x021B002C 0x000026D2
 DATA 4 0x021B0030 0x006B1023
-DATA 4 0x021B0040 0x00000047
-DATA 4 0x021B0000 0x83180000
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
 DATA 4 0x021B001C 0x02008032
 DATA 4 0x021B001C 0x00008033
 DATA 4 0x021B001C 0x00048031
diff --git a/board/technexion/picosom-imx6ul/picosom-imx6ul.c b/board/technexion/picosom-imx6ul/picosom-imx6ul.c
index e9e8cb1..ddbbeec 100644
--- a/board/technexion/picosom-imx6ul/picosom-imx6ul.c
+++ b/board/technexion/picosom-imx6ul/picosom-imx6ul.c
@@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define VERSION_DET_DDR_SIZE   IMX_GPIO_NR(5, 1)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C2 for PMIC */
@@ -142,6 +144,11 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
     MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const version_detection_pads[] = {
+	/* dram size detection */
+	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 #ifdef CONFIG_SYS_USE_NAND
 static iomux_v3_cfg_t const nand_pads[] = {
 	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
@@ -230,6 +237,11 @@ static void setup_iomux_fec(int fec_id)
 }
 #endif
 
+static void setup_iomux_version_detection(void)
+{
+	SETUP_IOMUX_PADS(version_detection_pads);
+}
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
@@ -706,9 +718,21 @@ u32 get_board_rev(void)
 	return get_cpu_rev();
 }
 
+void version_detection(void)
+{
+	setup_iomux_version_detection();
+	gpio_direction_input(VERSION_DET_DDR_SIZE);
+
+	if (gpio_get_value(VERSION_DET_DDR_SIZE))
+		printf("DRAM size is 512MB \r\n");
+	else
+		printf("DRAM size is 256MB \r\n");
+}
+
 int checkboard(void)
 {
-    puts("Board: PicoSOM i.mx6UL\n");
+	version_detection();
+	puts("Board: PicoSOM i.mx6UL\n");
 
 	return 0;
 }
-- 
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