From f59b55a5b8fcadaa99781ba48e7a38e956afa527 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Nov 2007 23:25:02 -0600 Subject: Stop using immap_t for guts offset on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala --- board/sbc8560/sbc8560.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'board/sbc8560/sbc8560.c') diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index e8b9929..e02fb55 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -264,7 +264,6 @@ long int initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if 0 #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc= &immap->im_lbc; @@ -273,7 +272,7 @@ long int initdram (int board_type) #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; -- cgit v1.1 From 04db400892da37b76a585e332a0c137954ad2015 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 02:10:09 -0600 Subject: Stop using immap_t on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala --- board/sbc8560/sbc8560.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'board/sbc8560/sbc8560.c') diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index e02fb55..47df884 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -266,7 +265,7 @@ long int initdram (int board_type) extern long spd_sdram (void); #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -335,8 +334,7 @@ long int initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -423,8 +421,7 @@ long int fixed_sdram (void) #define CFG_DDR_CONTROL 0xc2000000 #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = 0x00000007; ddr->cs1_bnds = 0x0010001f; -- cgit v1.1