From e4430779623af500de1cee7892c379f07ef59813 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 19:29:48 +0100 Subject: sh: lowlevel_init coding style cleanup Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/rsk7203/lowlevel_init.S | 214 +++++++++++++++++----------------- 1 file changed, 107 insertions(+), 107 deletions(-) (limited to 'board/renesas/rsk7203/lowlevel_init.S') diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e..f6a6231 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -29,153 +29,153 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 + mov.l CCR1_A, r1 + mov.l CCR1_D, r0 + mov.l r0, @r1 /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 + mov.l PECRL3_A, r1 + mov.l PECRL3_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D0, r0 + mov.w r0, @r1 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D0, r0 + mov.w r0, @r1 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 + mov.l PCIORL_A, r1 + mov.l PCIORL_D, r0 + mov.w r0, @r1 - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 + mov.l PFCRH2_A, r1 + mov.l PFCRH2_D, r0 + mov.w r0, @r1 - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 + mov.l PFCRH3_A, r1 + mov.l PFCRH3_D, r0 + mov.w r0, @r1 - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 + mov.l PFCRH1_A, r1 + mov.l PFCRH1_D, r0 + mov.w r0, @r1 - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 + mov.l PFIORH_A, r1 + mov.l PFIORH_D, r0 + mov.w r0, @r1 - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D1, r0 + mov.w r0, @r1 /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D0, r0 + mov.w r0, @r1 - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D1, r0 + mov.w r0, @r1 - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D1, r0 + mov.w r0, @r1 - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D1, r0 + mov.w r0, @r1 - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 + mov.l SC0BCR_A, r1 + mov.l SC0BCR_D, r0 + mov.l r0, @r1 - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D1, r0 + mov.w r0, @r1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 + mov.l PCCRL2_A, r1 + mov.l PCCRL2_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D2, r0 + mov.w r0, @r1 - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 + mov.l PCCRL1_A, r1 + mov.l PCCRL1_D, r0 + mov.w r0, @r1 - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 + mov.l PCCRL3_A, r1 + mov.l PCCRL3_D, r0 + mov.w r0, @r1 - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 + mov.l SDCR_A, r1 + mov.l SDCR_D, r0 + mov.l r0, @r1 - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 + mov.l REPEAT_D, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 nop rts @@ -208,8 +208,8 @@ PECRL1_D0: .long 0x00000033 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .long 0x0000A518 +WTCSR_D1: .long 0x0000A51D WTCNT_A: .long 0xFFFE0002 WTCNT_D: .long 0x00005A84 FRQCR_A: .long 0xFFFE0010 @@ -259,7 +259,7 @@ STBCR4_A: .long 0xFFFE040C STBCR4_D: .long 0x00000008 STBCR5_A: .long 0xFFFE0410 STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 +STBCR6_A: .long 0xFFFE0414 STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 -- cgit v1.1 From f7e78f3b74aae9caca2997bad865a72338326c0a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 19:29:49 +0100 Subject: sh: use write{8,16,32} in all lowlevel_init Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/rsk7203/lowlevel_init.S | 129 +++++++++------------------------- 1 file changed, 33 insertions(+), 96 deletions(-) (limited to 'board/renesas/rsk7203/lowlevel_init.S') diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index f6a6231..7b9ecd8 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -21,6 +21,7 @@ #include #include +#include .global lowlevel_init @@ -29,140 +30,76 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A, r1 - mov.l CCR1_D, r0 - mov.l r0, @r1 + write32 CCR1_A ,CCR1_D /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0, @r1 + write16 PECRL3_A, PECRL3_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D0 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0, @r1 + write16 PECRL4_A, PECRL4_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0, @r1 + write16 PEIORL_A, PEIORL_D0 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0, @r1 + write16 PCIORL_A, PCIORL_D - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0, @r1 + write16 PFCRH2_A, PFCRH2_D - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0, @r1 + write16 PFCRH3_A, PFCRH3_D - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0, @r1 + write16 PFCRH1_A, PFCRH1_D - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0, @r1 + write16 PFIORH_A, PFIORH_D - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0, @r1 + write16 PECRL1_A, PECRL1_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0, @r1 + write16 PEIORL_A, PEIORL_D1 /* Configure Operating Frequency */ - mov.l WTCSR_A, r1 - mov.l WTCSR_D0, r0 - mov.w r0, @r1 + write16 WTCSR_A, WTCSR_D0 - mov.l WTCSR_A, r1 - mov.l WTCSR_D1, r0 - mov.w r0, @r1 + write16 WTCSR_A, WTCSR_D1 - mov.l WTCNT_A, r1 - mov.l WTCNT_D, r0 - mov.w r0, @r1 + write16 WTCNT_A, WTCNT_D /* Set clock mode*/ - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.w r0, @r1 + write16 FRQCR_A, FRQCR_D /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D1, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D1 - mov.l PECRL1_A, r1 - mov.l PECRL1_D1, r0 - mov.w r0, @r1 + write16 PECRL1_A, PECRL1_D1 - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 + write32 CMNCR_A, CMNCR_D - mov.l SC0BCR_A, r1 - mov.l SC0BCR_D, r0 - mov.l r0, @r1 + write32 SC0BCR_A, SC0BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D init_bsc_cs1: - mov.l PECRL4_A, r1 - mov.l PECRL4_D1, r0 - mov.w r0, @r1 + write16 PECRL4_A, PECRL4_D1 - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 + write32 CS1WCR_A, CS1WCR_D init_sdram: - mov.l PCCRL2_A, r1 - mov.l PCCRL2_D, r0 - mov.w r0, @r1 + write16 PCCRL2_A, PCCRL2_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D2, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D2 - mov.l PCCRL1_A, r1 - mov.l PCCRL1_D, r0 - mov.w r0, @r1 + write16 PCCRL1_A, PCCRL1_D - mov.l PCCRL3_A, r1 - mov.l PCCRL3_D, r0 - mov.w r0, @r1 + write16 PCCRL3_A, PCCRL3_D - mov.l CS3BCR_A, r1 - mov.l CS3BCR_D, r0 - mov.l r0, @r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A, r1 - mov.l CS3WCR_D, r0 - mov.l r0, @r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A, r1 - mov.l SDCR_D, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D - mov.l RTCOR_A, r1 - mov.l RTCOR_D, r0 - mov.l r0, @r1 + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A, r1 - mov.l RTCSR_D, r0 - mov.l r0, @r1 + write32 RTCSR_A, RTCSR_D /* wait 200us */ mov.l REPEAT_D, r3 -- cgit v1.1