From 0bf51cb032b7863f41e5f3043cd215426197a98e Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 9 Dec 2014 11:24:01 +0900 Subject: arm: rmobile: koelsch: Migrate serial driver to drivers model This adds drivers model support of serial port to Koelsch board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'board/renesas/koelsch') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 10fa571..f627433 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -9,6 +9,8 @@ #include #include +#include +#include #include #include #include @@ -160,3 +162,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF0_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(koelsch_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; -- cgit v1.1 From 11e329106bc92765f8fa68ff9777f79a69d98721 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 12 Nov 2014 13:03:54 +0900 Subject: arm: rmobile: koelsch: Add support SDHI Koelsch board has three SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 72 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'board/renesas/koelsch') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index f627433..51e70e2 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,14 @@ void s_init(void) #define SCIF0_MSTP721 (1 << 21) #define ETHER_MSTP813 (1 << 13) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) +#define SDHI2_MSTP311 (1 << 11) + +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); @@ -60,6 +69,17 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* SDHI */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, + SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 and SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); + return 0; } @@ -128,6 +148,58 @@ int board_eth_init(bd_t *bis) #endif } +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DATA0, NULL); + gpio_request(GPIO_FN_SD2_DATA1, NULL); + gpio_request(GPIO_FN_SD2_DATA2, NULL); + gpio_request(GPIO_FN_SD2_DATA3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_7_17, NULL); + gpio_request(GPIO_GP_2_12, NULL); + gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_7_18, NULL); + gpio_request(GPIO_GP_2_13, NULL); + gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_7_19, NULL); + gpio_request(GPIO_GP_2_26, NULL); + gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -- cgit v1.1