From 6a7b52bc8d30090633d098f9e988276beb7a53d5 Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Wed, 16 Mar 2016 16:59:59 +0800 Subject: mips: ath79: add AP121 reference board This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck --- board/qca/ap121/Kconfig | 12 +++++++++++ board/qca/ap121/MAINTAINERS | 6 ++++++ board/qca/ap121/Makefile | 5 +++++ board/qca/ap121/ap121.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 board/qca/ap121/Kconfig create mode 100644 board/qca/ap121/MAINTAINERS create mode 100644 board/qca/ap121/Makefile create mode 100644 board/qca/ap121/ap121.c (limited to 'board/qca') diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig new file mode 100644 index 0000000..f7e768a --- /dev/null +++ b/board/qca/ap121/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP121 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap121" + +config SYS_CONFIG_NAME + default "ap121" + +endif diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS new file mode 100644 index 0000000..8b02988 --- /dev/null +++ b/board/qca/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang +S: Maintained +F: board/qca/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile new file mode 100644 index 0000000..ced5432 --- /dev/null +++ b/board/qca/ap121/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c new file mode 100644 index 0000000..d6c60fe --- /dev/null +++ b/board/qca/ap121/ap121.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015-2016 Wills Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val &= ~AR933X_GPIO(9); + val |= AR933X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO + */ + val = readl(regs + AR71XX_GPIO_REG_FUNC); + val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; + writel(val, regs + AR71XX_GPIO_REG_FUNC); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} -- cgit v1.1