From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/prodrive/p3p440/config.mk | 2 +- board/prodrive/p3p440/init.S | 12 ++++++------ board/prodrive/p3p440/p3p440.c | 32 ++++++++++++++++---------------- board/prodrive/p3p440/p3p440.h | 10 +++++----- 4 files changed, 28 insertions(+), 28 deletions(-) (limited to 'board/prodrive/p3p440') diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk index e5722dd..60d3bf4 100644 --- a/board/prodrive/p3p440/config.mk +++ b/board/prodrive/p3p440/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S index ee6b706..8c1a79c 100644 --- a/board/prodrive/p3p440/init.S +++ b/board/prodrive/p3p440/init.S @@ -90,10 +90,10 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a8aacb..1a0486f 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -35,29 +35,29 @@ void set_led(int color) { switch (color) { case LED_OFF: - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED); break; case LED_GREEN: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED); + out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED); break; case LED_RED: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN); + out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN); break; case LED_ORANGE: - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED); break; } } static int is_monarch(void) { - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY); udelay(1000); - if (in32(GPIO0_IR) & CFG_MONARCH_IO) + if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO) return 0; else return 1; @@ -68,11 +68,11 @@ static void wait_for_pci_ready(void) /* * Configure EREADY_IO as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO); udelay(1000); for (;;) { - if (in32(GPIO0_IR) & CFG_EREADY_IO) + if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO) return; } @@ -95,8 +95,8 @@ int board_early_init_f(void) mtdcr(cpc0_gpio, 0x03F01F80); out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN); - out32(GPIO0_OR, CFG_GPIO_RDY); + out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); + out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -152,7 +152,7 @@ int misc_init_r (void) /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { mtebc(pb1cr, 0); /* disable cs */ mtebc(pb1ap, 0); mtebc(pb2cr, 0); /* disable cs */ @@ -203,7 +203,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -218,7 +218,7 @@ void pci_target_init(struct pci_controller *hose) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); out32r(PCIX0_PIM0LAH, 0); out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); @@ -227,12 +227,12 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h index e4e87d1..47e9018 100644 --- a/board/prodrive/p3p440/p3p440.h +++ b/board/prodrive/p3p440/p3p440.h @@ -24,11 +24,11 @@ #ifndef __P3P440_H__ #define __P3P440_H__ -#define CFG_GPIO_RDY (0x80000000 >> 11) -#define CFG_MONARCH_IO (0x80000000 >> 18) -#define CFG_EREADY_IO (0x80000000 >> 20) -#define CFG_LED_GREEN (0x80000000 >> 21) -#define CFG_LED_RED (0x80000000 >> 22) +#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11) +#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18) +#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20) +#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21) +#define CONFIG_SYS_LED_RED (0x80000000 >> 22) #define LED_OFF 1 #define LED_GREEN 2 -- cgit v1.1 From 9b827cf1720acda2473afa516956eab6f7cca9a1 Mon Sep 17 00:00:00 2001 From: Selvamuthukumar Date: Thu, 16 Oct 2008 22:54:03 +0530 Subject: Align end of bss by 4 bytes Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar Signed-off-by: Wolfgang Denk --- board/prodrive/p3p440/u-boot.lds | 1 + 1 file changed, 1 insertion(+) (limited to 'board/prodrive/p3p440') diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 0e6c878..17cfde8 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); -- cgit v1.1