From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/prodrive/alpr/alpr.c | 34 ++++++++++----------- board/prodrive/alpr/config.mk | 2 +- board/prodrive/alpr/fpga.c | 70 +++++++++++++++++++++---------------------- board/prodrive/alpr/init.S | 24 +++++++-------- board/prodrive/alpr/nand.c | 2 +- 5 files changed, 66 insertions(+), 66 deletions(-) (limited to 'board/prodrive/alpr') diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index cc491d0..dc34319 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -92,8 +92,8 @@ int board_early_init_f (void) mtdcr (uic0vr, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); /* Setup GPIO/IRQ multiplexing */ mtsdr(sdr_pfc0, 0x01a33e00); @@ -124,8 +124,8 @@ int last_stage_init(void) static int board_rev(void) { /* Setup as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); return (in32(GPIO0_IR) >> 16) & 0x3; } @@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -201,7 +201,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -210,12 +210,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host @@ -239,11 +239,11 @@ static void wait_for_pci_ready(void) /* * Configure EREADY as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); udelay(1000); for (;;) { - if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) return; } @@ -260,7 +260,7 @@ int is_pci_host(struct pci_controller *hose) * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -274,19 +274,19 @@ void pci_master_init(struct pci_controller *hose) out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ - out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ #ifdef CONFIG_POST /* diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk index 9e18335..b62e776 100644 --- a/board/prodrive/alpr/config.mk +++ b/board/prodrive/alpr/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index e94360f..0ecebc9 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -61,10 +61,10 @@ static unsigned long regval; #define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) #define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) -#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) -#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) -#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) -#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) +#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN) +#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG) +#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA) +#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK) #define OLD_VAL (FPGA_PRG | FPGA_CONFIG) #define SET_FPGA(data) out32(GPIO0_OR, data) @@ -87,43 +87,43 @@ int fpga_pre_fn (int cookie) reg = in32(GPIO0_IR); /* Enable the FPGA Chain */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); - SET_GPIO_1(CFG_GPIO_PROG_EN); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); - SET_GPIO_0((CFG_GPIO_SEL_DPR)); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR); + SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR)); /* initialize the GPIO Pins */ /* output */ - SET_GPIO_0(CFG_GPIO_CLK); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); + SET_GPIO_0(CONFIG_SYS_GPIO_CLK); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK); /* output */ - SET_GPIO_0(CFG_GPIO_DATA); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); + SET_GPIO_0(CONFIG_SYS_GPIO_DATA); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA); /* First we set STATUS to 0 then as an input */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); - SET_GPIO_0(CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_0(CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); /* output */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); /* input */ - SET_GPIO_0(CFG_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); + SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON); /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); return FPGA_SUCCESS; } @@ -131,9 +131,9 @@ int fpga_pre_fn (int cookie) int fpga_config_fn (int assert_config, int flush, int cookie) { if (assert_config) { - SET_GPIO_1(CFG_GPIO_CONFIG); + SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG); } else { - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); } return FPGA_SUCCESS; } @@ -144,7 +144,7 @@ int fpga_status_fn (int cookie) unsigned long reg; reg = in32(GPIO0_IR); - if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { + if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) { PRINTF("STATUS = HIGH\n"); return FPGA_FAIL; } @@ -157,7 +157,7 @@ int fpga_done_fn (int cookie) { unsigned long reg; reg = in32(GPIO0_IR); - if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { + if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) { PRINTF("CONF_DON = HIGH\n"); return FPGA_FAIL; } @@ -189,10 +189,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) i --; } while (i > 0); -#ifdef CFG_FPGA_PROG_FEEDBACK +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % len_40 == 0) { putc ('.'); /* let them know we are alive */ -#ifdef CFG_FPGA_CHECK_CTRLC +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC if (ctrlc ()) return FPGA_FAIL; #endif @@ -205,7 +205,7 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) /* called, when programming is aborted */ int fpga_abort_fn (int cookie) { - SET_GPIO_1((CFG_GPIO_SEL_DPR)); + SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR)); return FPGA_SUCCESS; } diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 76164ce..4af7d13 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -87,26 +87,26 @@ tlbtab: tlbtab_start tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) #ifdef CONFIG_4xx_DCACHE - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) /* NAND */ - tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 99f5737..b18c96b 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -137,7 +137,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; + alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE; nand->ecc.mode = NAND_ECC_SOFT; -- cgit v1.1