From d07dc4993d646a1b1857a987f9145bf0a8c21370 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 30 Aug 2011 06:23:15 +0000 Subject: Tegra2: Use clock and pinmux functions to simplify code Signed-off-by: Simon Glass --- board/nvidia/common/board.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'board/nvidia/common') diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 799dd3a..160dac8 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -81,20 +81,20 @@ static void clock_init_uart(void) u32 reg; reg = readl(&pll->pll_base); - if (!(reg & PLL_BASE_OVRRIDE)) { + if (!(reg & PLL_BASE_OVRRIDE_MASK)) { /* Override pllp setup for 216MHz operation. */ - reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE); - reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE); + reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK | + (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT); + reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT; writel(reg, &pll->pll_base); - reg |= PLL_ENABLE; + reg |= PLL_ENABLE_MASK; writel(reg, &pll->pll_base); - reg &= ~PLL_BYPASS; + reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); } - /* Now do the UART reset/clock enable */ #if defined(CONFIG_TEGRA2_ENABLE_UARTA) /* Assert UART reset and enable clock */ reset_set_enable(PERIPH_ID_UART1, 1); -- cgit v1.1