From bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:37:28 +0200 Subject: ppc4xx: Remove superfluous dram_init() call or replace it by initdram() Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese --- board/netstal/hcu5/sdram.c | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) (limited to 'board/netstal/hcu5/sdram.c') diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 6b1b53a..d8817b8 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -40,28 +40,6 @@ void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) - #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -111,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(memcfga, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(memcfgd); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ -- cgit v1.1