From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- board/mpc8641hpcn/Makefile | 57 +++++ board/mpc8641hpcn/config.mk | 32 +++ board/mpc8641hpcn/flash.c | 550 ++++++++++++++++++++++++++++++++++++++++ board/mpc8641hpcn/init.S | 172 +++++++++++++ board/mpc8641hpcn/mpc8641hpcn.c | 315 +++++++++++++++++++++++ board/mpc8641hpcn/oftree.dts | 186 ++++++++++++++ board/mpc8641hpcn/u-boot.lds | 148 +++++++++++ 7 files changed, 1460 insertions(+) create mode 100644 board/mpc8641hpcn/Makefile create mode 100644 board/mpc8641hpcn/config.mk create mode 100644 board/mpc8641hpcn/flash.c create mode 100644 board/mpc8641hpcn/init.S create mode 100644 board/mpc8641hpcn/mpc8641hpcn.c create mode 100644 board/mpc8641hpcn/oftree.dts create mode 100644 board/mpc8641hpcn/u-boot.lds (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile new file mode 100644 index 0000000..d6037c1 --- /dev/null +++ b/board/mpc8641hpcn/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o oftree.o +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +%.dtb: %.dts + dtc -f -V 0x10 -I dts -O dtb $< >$@ + +%.c: %.dtb + xxd -i $< \ + | sed -e "s/^unsigned char/const unsigned char/g" \ + | sed -e "s/^unsigned int/const unsigned int/g" > $@ + + +clean: + rm -f $(OBJS) $(SOBJS) *.dtb oftree.c +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +ifeq ($(filter distclean, $(MAKECMDGOALS)),) +-include .depend +endif + +######################################################################### diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk new file mode 100644 index 0000000..63b9779 --- /dev/null +++ b/board/mpc8641hpcn/config.mk @@ -0,0 +1,32 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown (jeffrey@freescale.com) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8641hpcn board +# default CCSRBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +#TEXT_BASE = 0xfff01000 +TEXT_BASE = 0x00400000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/flash.c b/board/mpc8641hpcn/flash.c new file mode 100644 index 0000000..e2f7816 --- /dev/null +++ b/board/mpc8641hpcn/flash.c @@ -0,0 +1,550 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao,(X.Xiao@motorola.com) + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if !defined(CFG_NO_FLASH) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#undef DEBUG + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(vu_long * addr); +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + ulong sector_offset; + +#ifdef DEBUG + printf("Check flash at 0x%08x\n",(uint)addr); +#endif + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + udelay(20); + asm("sync"); + + value = addr[0] & 0x00FF00FF; + +#ifdef DEBUG + printf("manufacturer=0x%x\n",(uint)value); +#endif + switch (value) { + case MT_MANUFACT: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU: + info->flash_id = FLASH_MAN_INTEL; + break; + default: +#if defined(CONFIG_MPC8641_SIM) + info->flash_id = FLASH_MAN_INTEL; + break; +#else + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ +#endif + } + + value = addr[1] & 0x00FF00FF; /* device ID */ + +#ifdef DEBUG + printf("deviceID=0x%x\n",(uint)value); +#endif + switch (value) { + case (INTEL_ID_28F016S): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + sector_offset = 0x20000; + break; /* => 2x4 MB */ + + case (INTEL_ID_28F640J3A): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + sector_offset = 0x40000; + break; /* => 2x8 MB */ + + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + info->size = 0x00800000; + sector_offset = 0x40000; + break; /* => 4x2 MB */ + + + default: +#if defined(CONFIG_MPC8641_SIM) + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + sector_offset = 0x40000; + break; /* => 2x8 MB */ +#else + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ +#endif + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + *addr = 0xFFFFFF; /* reset bank to read array mode */ + asm("sync"); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + printf("\nFlash Erase:\n"); +#endif + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ + return 1; + } + + /* Start erase on unprotected sectors */ +#if defined(DEBUG) + printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); +#endif + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + asm("sync"); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + /* Single Block Erase Command */ + *addr = 0x20202020; + asm("sync"); + /* Confirm */ + *addr = 0xD0D0D0D0; + asm("sync"); + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + asm("sync"); + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + while ((*addr & 0x00800080) != 0x00800080) { + if(*addr & 0x00200020){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + } + } + + printf ("flash erase done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + asm("sync"); + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + + while (((csr = *addr) & 0x00800080) != 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(vu_long * addr) +{ + ulong start, now; + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + + *addr = 0x60606060; + asm("sync"); + *addr = 0xd0d0d0d0; + asm("sync"); + + start = get_timer (0); + while((*addr & 0x00800080) != 0x00800080){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + } + return 0; +} + +#endif /* !CFG_NO_FLASH */ diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S new file mode 100644 index 0000000..9d43de5 --- /dev/null +++ b/board/mpc8641hpcn/init.S @@ -0,0 +1,172 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR1 0 +#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ +#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) +/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ +#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) + + #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) + #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +/* +#ifdef CFG_INIT_RAM_LOCK +#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#endif +*/ +/* + * Stack at 0xfc00_0000 for 32M on LBC + */ +#if !defined(CFG_INIT_RAM_LOCK) +#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#endif + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + blr + diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c new file mode 100644 index 0000000..cdfce6c --- /dev/null +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -0,0 +1,315 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts("Board: MPC8641HPCN\n"); + +#ifdef CONFIG_PCI + + /* Sri: Note that at this point we will only test on PCI1 + */ + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + + if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + } + debug ("\n"); + } else { + printf ("PCI-EXPRESS 1: Disabled\n"); + } + +#else + printf("PCI-EXPRESS1: Disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. Currently HPCN doesn't have + * SDRAM but we'll leave this here for now + * in case someone changes their mind + */ +#if !defined(CONFIG_MPC8641HPCN) + // sdram_init(); +#endif + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000008D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync"); + + udelay(500); + +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg_1 = CFG_DDR_CONTROL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; +#endif + asm("sync; isync"); + + udelay(500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init(struct pci_controller *hose); + + pci_mpc86xx_init(&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } + +} +#endif + +void +after_reloc(ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* now, jump to the main U-Boot board init code */ + board_init_r ((gd_t *)gd, dest_addr); + + /* NOTREACHED */ +} + + + diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts new file mode 100644 index 0000000..6c32ade --- /dev/null +++ b/board/mpc8641hpcn/oftree.dts @@ -0,0 +1,186 @@ +/* + * MPC8641 HPCn Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +/ { + model = "MPC8641HPCN"; + compatible = "mpc86xx"; + #address-cells = <1>; + #size-cells = <1>; + linux,phandle = <100>; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + linux,phandle = <200>; + + PowerPC,8641@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // 166 MHz + clock-frequency = <0>; // 825 MHz, from uboot + 32-bit; + linux,phandle = <201>; + linux,boot-cpu; + }; + }; + + memory { + device_type = "memory"; + linux,phandle = <300>; + reg = <00000000 10000000>; // 256M at 0x0 + }; + + soc8641@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <2>; + device_type = "soc"; + ranges = <0 f8000000 00100000>; + reg = ; // CCSRBAR 1M + bus-frequency = <0>; + + i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <1b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "gianfar"; + reg = <24520 20>; + linux,phandle = <24520>; + ethernet-phy@0 { + linux,phandle = <2452000>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <0>; + device_type = "ethernet-phy"; + }; + ethernet-phy@1 { + linux,phandle = <2452001>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <1>; + device_type = "ethernet-phy"; + }; + ethernet-phy@2 { + linux,phandle = <2452002>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <2>; + device_type = "ethernet-phy"; + }; + ethernet-phy@3 { + linux,phandle = <2452003>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + ethernet@24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <24000 1000>; + address = [ 00 E0 0C 00 73 00 ]; + interrupts = ; + interrupt-parent = <40000>; + phy-handle = <2452000>; + }; + + ethernet@25000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <25000 1000>; + address = [ 00 E0 0C 00 73 01 ]; + interrupts = <13 3 14 3 18 3>; + interrupt-parent = <40000>; + phy-handle = <2452001>; + }; + + ethernet@26000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <26000 1000>; + address = [ 00 E0 0C 00 02 FD ]; + interrupts = ; + interrupt-parent = <40000>; + phy-handle = <2452002>; + }; + + ethernet@27000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <27000 1000>; + address = [ 00 E0 0C 00 03 FD ]; + interrupts = <15 3 16 3 17 3>; + interrupt-parent = <40000>; + phy-handle = <2452003>; + }; + serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4500 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + interrupts = <1a 3>; + interrupt-parent = <40000>; + }; + + serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4600 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + interrupts = <1a 3>; + interrupt-parent = <40000>; + }; + + pic@40000 { + linux,phandle = <40000>; + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + built-in; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; +}; + diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds new file mode 100644 index 0000000..dbe8e4f --- /dev/null +++ b/board/mpc8641hpcn/u-boot.lds @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2004, Freescale, Inc. + * (C) Copyright 2002,2003, Motorola,Inc. + * Jeff Brown (jeffrey@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* .resetvec 0xFFF00100 : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFF70000 : + { + cpu/mpc86xx/start.o (.bootpg) + board/mpc8641hpcn/init.o (.bootpg) + } = 0xffff +*/ + /* Read-only sections, merged into text segment: */ + . = + 1024; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/mpc8641hpcn/init.o (.text) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + cpu/mpc86xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 10:15:16 -0500 Subject: Cleanup whitespaces and style issues. Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. --- board/mpc8641hpcn/mpc8641hpcn.c | 33 ++++++++++++--------------------- board/mpc8641hpcn/oftree.dts | 2 +- 2 files changed, 13 insertions(+), 22 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index cdfce6c..ace6d47 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -57,9 +57,6 @@ int checkboard (void) #ifdef CONFIG_PCI - /* Sri: Note that at this point we will only test on PCI1 - */ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_pex_t *pex1 = &immap->im_pex1; @@ -70,13 +67,16 @@ int checkboard (void) uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); + if ((io_sel==2 || io_sel==3 || io_sel==5 \ + || io_sel==6 || io_sel==7 || io_sel==0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } else { @@ -120,15 +120,6 @@ initdram(int board_type) ddr_enable_ecc(dram_size); #endif - /* - * Initialize SDRAM. Currently HPCN doesn't have - * SDRAM but we'll leave this here for now - * in case someone changes their mind - */ -#if !defined(CONFIG_MPC8641HPCN) - // sdram_init(); -#endif - puts(" DDR: "); return dram_size; } @@ -163,7 +154,7 @@ local_bus_init(void) } #if defined(CFG_DRAM_TEST) -int testdram (void) +int testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -198,10 +189,10 @@ int testdram (void) #if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram(void) { #if !defined(CFG_RAMBOOT) volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 6c32ade..8e38047 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -1,5 +1,5 @@ /* - * MPC8641 HPCn Device Tree Source + * MPC8641 HPCN Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * -- cgit v1.1 From 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 9 May 2006 08:23:49 -0500 Subject: Get MPC8641HPCN flash images working. Enable the CFI driver. Remove bogus LAWBAR7 cruft. Use correct TEXT_BASE, Fixup load script. Enable SPD EEPROM during DDR setup. Use generic RFC 1918 IP addresses by default. --- board/mpc8641hpcn/config.mk | 3 +-- board/mpc8641hpcn/init.S | 17 ----------------- board/mpc8641hpcn/u-boot.lds | 4 ++-- 3 files changed, 3 insertions(+), 21 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 63b9779..4bdceec 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -25,8 +25,7 @@ # default CCSRBAR is at 0xff700000 # assume U-Boot is less than 0.5MB # -#TEXT_BASE = 0xfff01000 -TEXT_BASE = 0x00400000 +TEXT_BASE = 0xfff01000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 9d43de5..4d555a5 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -80,23 +80,6 @@ #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -/* -#ifdef CFG_INIT_RAM_LOCK -#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#endif -*/ -/* - * Stack at 0xfc00_0000 for 32M on LBC - */ -#if !defined(CFG_INIT_RAM_LOCK) -#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -#endif - .section .bootpg, "ax" .globl law_entry law_entry: diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index dbe8e4f..c5c40e7 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -28,7 +28,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/ __DYNAMIC = 0; */ SECTIONS { -/* .resetvec 0xFFF00100 : + .resetvec 0xFFF00100 : { *(.resetvec) } = 0xffff @@ -38,7 +38,7 @@ SECTIONS cpu/mpc86xx/start.o (.bootpg) board/mpc8641hpcn/init.o (.bootpg) } = 0xffff -*/ + /* Read-only sections, merged into text segment: */ . = + 1024; .interp : { *(.interp) } -- cgit v1.1 From d4dd317b58c126a2a7e73f4764ecc1a7c97f876c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 10 May 2006 09:33:07 -0500 Subject: Remove unnecessary flash.c file. --- board/mpc8641hpcn/flash.c | 550 ---------------------------------------------- 1 file changed, 550 deletions(-) delete mode 100644 board/mpc8641hpcn/flash.c (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/flash.c b/board/mpc8641hpcn/flash.c deleted file mode 100644 index e2f7816..0000000 --- a/board/mpc8641hpcn/flash.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: -#if defined(CONFIG_MPC8641_SIM) - info->flash_id = FLASH_MAN_INTEL; - break; -#else - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ -#endif - } - - value = addr[1] & 0x00FF00FF; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: -#if defined(CONFIG_MPC8641_SIM) - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ -#else - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ -#endif - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if(*addr & 0x00200020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ -- cgit v1.1 From 6cfea33477b04b63ed47386ed1629529484c33ba Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 May 2006 09:38:06 -0500 Subject: Remove unneeded INIT_RAM_LOCK cache twiddling. Correctly tracks r29 as global data pointer now. Signed-off-by: Haiying Wang --- board/mpc8641hpcn/mpc8641hpcn.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index ace6d47..d02a7ef 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -291,16 +291,5 @@ ft_board_setup(void *blob, bd_t *bd) } #endif -void -after_reloc(ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - -- cgit v1.1 From bf690dcb512d34c4fceec0eb1e5c0e88a9db5d54 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 15 May 2006 07:26:56 -0500 Subject: Update interrupt mapping. --- board/mpc8641hpcn/oftree.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 8e38047..ef28fc3 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -58,7 +58,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3000 100>; - interrupts = <1b 0>; + interrupts = <2b 0>; interrupt-parent = <40000>; dfsrr; }; @@ -73,28 +73,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <3>; device_type = "ethernet-phy"; }; @@ -108,7 +108,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = ; + interrupts = <1d 3 1e 3 22 3>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -121,7 +121,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <13 3 14 3 18 3>; + interrupts = <23 3 24 3 28 3>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -134,7 +134,7 @@ compatible = "gianfar"; reg = <26000 1000>; address = [ 00 E0 0C 00 02 FD ]; - interrupts = ; + interrupts = <1F 3 20 3 21 3>; interrupt-parent = <40000>; phy-handle = <2452002>; }; @@ -147,7 +147,7 @@ compatible = "gianfar"; reg = <27000 1000>; address = [ 00 E0 0C 00 03 FD ]; - interrupts = <15 3 16 3 17 3>; + interrupts = <25 3 26 3 27 3>; interrupt-parent = <40000>; phy-handle = <2452003>; }; @@ -156,7 +156,7 @@ compatible = "ns16550"; reg = <4500 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <2a 3>; interrupt-parent = <40000>; }; @@ -165,7 +165,7 @@ compatible = "ns16550"; reg = <4600 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <2a 3>; interrupt-parent = <40000>; }; -- cgit v1.1 From f35ec68fb066cec0e36294bfe07dec2d4e8ad3a8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 12:33:09 -0500 Subject: Enable 2nd CPU and I2C. --- board/mpc8641hpcn/oftree.dts | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index ef28fc3..d4e40b8 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -18,7 +18,7 @@ linux,phandle = <100>; cpus { - #cpus = <1>; + #cpus = <2>; #address-cells = <1>; #size-cells = <0>; linux,phandle = <200>; @@ -31,18 +31,31 @@ d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // 166 MHz - clock-frequency = <0>; // 825 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot 32-bit; linux,phandle = <201>; linux,boot-cpu; }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + 32-bit; + linux,phandle = <202>; + }; }; memory { device_type = "memory"; linux,phandle = <300>; - reg = <00000000 10000000>; // 256M at 0x0 + reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot }; soc8641@f8000000 { @@ -63,6 +76,15 @@ dfsrr; }; + i2c@3100 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3100 100>; + interrupts = <2b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:22:44 -0500 Subject: Update 86xx address map and LAWBARs. --- board/mpc8641hpcn/init.S | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 4d555a5..5f19fdf 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -36,11 +36,10 @@ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: @@ -76,9 +75,16 @@ /*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) - #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) - #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif .section .bootpg, "ax" .globl law_entry @@ -151,5 +157,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + blr -- cgit v1.1 From ed45d6c930b5939718a87ee12e25cf9a05978d4a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 26 May 2006 10:13:04 -0500 Subject: Added pci@8000 block. Updated ethernet interrupt mappings (moved up 48). Cleaned up a few comments. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/oftree.dts | 130 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 119 insertions(+), 11 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index d4e40b8..26ce661 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -30,7 +30,7 @@ i-cache-line-size = <20>; // 32 bytes d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot + timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot 32-bit; @@ -44,7 +44,7 @@ i-cache-line-size = <20>; // 32 bytes d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot + timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot 32-bit; @@ -55,7 +55,7 @@ memory { device_type = "memory"; linux,phandle = <300>; - reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot + reg = <00000000 40000000>; // 1G at 0x0 }; soc8641@f8000000 { @@ -95,28 +95,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <3>; device_type = "ethernet-phy"; }; @@ -176,8 +176,8 @@ serial@4500 { device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4500 100>; + clock-frequency = <0>; interrupts = <2a 3>; interrupt-parent = <40000>; }; @@ -185,12 +185,120 @@ serial@4600 { device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4600 100>; + clock-frequency = <0>; interrupts = <2a 3>; interrupt-parent = <40000>; }; + pci@8000 { + compatible = "86xx"; + device_type = "pci"; + linux,phandle = <8000>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + bus-range = <0 fe>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <40000>; + interrupts = <8 0>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 */ + 8800 0 0 1 40000 3 0 + 8800 0 0 2 40000 4 0 + 8800 0 0 3 40000 5 0 + 8800 0 0 4 40000 6 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 4 0 + 9000 0 0 2 40000 5 0 + 9000 0 0 3 40000 6 0 + 9000 0 0 4 40000 3 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 5 0 + 9800 0 0 2 40000 6 0 + 9800 0 0 3 40000 3 0 + 9800 0 0 4 40000 4 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 6 0 + a000 0 0 2 40000 3 0 + a000 0 0 3 40000 4 0 + a000 0 0 4 40000 5 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 0 0 + a800 0 0 2 40000 0 0 + a800 0 0 3 40000 0 0 + a800 0 0 4 40000 0 0 + + /* IDSEL 0x16 */ + b000 0 0 1 40000 0 0 + b000 0 0 2 40000 0 0 + b000 0 0 3 40000 0 0 + b000 0 0 4 40000 0 0 + + /* IDSEL 0x17 */ + b800 0 0 1 40000 0 0 + b800 0 0 2 40000 0 0 + b800 0 0 3 40000 0 0 + b800 0 0 4 40000 0 0 + + /* IDSEL 0x18 */ + c000 0 0 1 40000 0 0 + c000 0 0 2 40000 0 0 + c000 0 0 3 40000 0 0 + c000 0 0 4 40000 0 0 + + /* IDSEL 0x19 */ + c800 0 0 1 40000 0 0 + c800 0 0 2 40000 0 0 + c800 0 0 3 40000 0 0 + c800 0 0 4 40000 0 0 + + /* IDSEL 0x1a */ + d000 0 0 1 40000 0 0 + d000 0 0 2 40000 0 0 + d000 0 0 3 40000 0 0 + d000 0 0 4 40000 0 0 + + + /* IDSEL 0x1b */ + d800 0 0 1 40000 0 0 + d800 0 0 2 40000 0 0 + d800 0 0 3 40000 0 0 + d800 0 0 4 40000 0 0 + + /* IDSEL 0x1c */ + e000 0 0 1 40000 0 0 + e000 0 0 2 40000 0 0 + e000 0 0 3 40000 0 0 + e000 0 0 4 40000 0 0 + + /* IDSEL 0x1d */ + e800 0 0 1 40000 0 0 + e800 0 0 2 40000 0 0 + e800 0 0 3 40000 0 0 + e800 0 0 4 40000 0 0 + + /* IDSEL 0x1e */ + f000 0 0 1 40000 0 0 + f000 0 0 2 40000 0 0 + f000 0 0 3 40000 0 0 + f000 0 0 4 40000 0 0 + + /* IDSEL 0x1f */ + f800 0 0 1 40000 6 0 + f800 0 0 2 40000 6 0 + f800 0 0 3 40000 6 0 + f800 0 0 4 40000 6 0 + >; + }; pic@40000 { linux,phandle = <40000>; clock-frequency = <0>; -- cgit v1.1 From 126aa70f10ba3d20e0a6f4d32328250513b77770 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 30 May 2006 17:47:00 -0500 Subject: Move mpc86xx PIXIS code to board directory First cut at moving the PIXIS platform code out of the 86xx cpu directory and into board/mpc8641hpcn where it belongs. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 2 +- board/mpc8641hpcn/pixis.c | 324 +++++++++++++++++++++++++++++++++++++++++++++ board/mpc8641hpcn/pixis.h | 33 +++++ 3 files changed, 358 insertions(+), 1 deletion(-) create mode 100644 board/mpc8641hpcn/pixis.c create mode 100644 board/mpc8641hpcn/pixis.h (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index d6037c1..2613730 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o oftree.o +OBJS := $(BOARD).o pixis.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c new file mode 100644 index 0000000..f226b3e --- /dev/null +++ b/board/mpc8641hpcn/pixis.c @@ -0,0 +1,324 @@ +/* + * Copyright 2006 Freescale Semiconductor + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "pixis.h" + + +/* + * Per table 27, page 58 of MPC8641HPCN spec. + */ +int set_px_sysclk(ulong sysclk) +{ + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; + + switch (sysclk) { + case 33: + sysclk_s = 0x04; + sysclk_r = 0x04; + sysclk_v = 0x07; + sysclk_aux = 0x00; + break; + case 40: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x20; + sysclk_aux = 0x01; + break; + case 50: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x2A; + sysclk_aux = 0x02; + break; + case 66: + sysclk_s = 0x01; + sysclk_r = 0x04; + sysclk_v = 0x04; + sysclk_aux = 0x03; + break; + case 83: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x04; + break; + case 100: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x5C; + sysclk_aux = 0x05; + break; + case 134: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x3B; + sysclk_aux = 0x06; + break; + case 166: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x07; + break; + default: + printf("Unsupported SYSCLK frequency.\n"); + return 0; + } + + vclkh = (sysclk_s << 5) | sysclk_r ; + vclkl = sysclk_v; + + out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); + out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); + + out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + + return 1; +} + + +int set_px_mpxpll(ulong mpxpll) +{ + u8 tmp; + u8 val; + + switch (mpxpll) { + case 2: + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + val = (u8)mpxpll; + break; + default: + printf("Unsupported MPXPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED1); + tmp = (tmp & 0xF0) | (val & 0x0F); + out8(PIXIS_BASE + PIXIS_VSPEED1, tmp); + + return 1; +} + + +int set_px_corepll(ulong corepll) +{ + u8 tmp; + u8 val; + + switch ((int)corepll) { + case 20: + val = 0x08; + break; + case 25: + val = 0x0C; + break; + case 30: + val = 0x10; + break; + case 35: + val = 0x1C; + break; + case 40: + val = 0x14; + break; + case 45: + val = 0x0E; + break; + default: + printf("Unsupported COREPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED0); + tmp = (tmp & 0xE0) | (val & 0x1F); + out8(PIXIS_BASE + PIXIS_VSPEED0, tmp); + + return 1; +} + + +void read_from_px_regs(int set) +{ + u8 mask = 0x1C; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp); +} + + +void read_from_px_regs_altbank(int set) +{ + u8 mask = 0x04; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); +} + + +void set_altbank(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp ^= 0x40; + + out8(PIXIS_BASE + PIXIS_VBOOT, tmp); +} + + +void set_px_go(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x01; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +void set_px_go_with_watchdog(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x09; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + /* setting VCTL[WDEN] to 0 to disable watch dog */ + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~ 0x08; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + return 0; +} + + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL +); + + +/* + * This function takes the non-integral cpu:mpx pll ratio + * and converts it to an integer that can be used to assign + * FPGA register values. + * input: strptr i.e. argv[2] + */ + +ulong strfractoint(uchar *strptr) +{ + int i, j, retval; + int mulconst; + int intarr_len = 0, decarr_len = 0, no_dec = 0; + ulong intval = 0, decval = 0; + uchar intarr[3], decarr[3]; + + /* Assign the integer part to intarr[] + * If there is no decimal point i.e. + * if the ratio is an integral value + * simply create the intarr. + */ + i = 0; + while (strptr[i] != 46) { + if (strptr[i] == 0) { + no_dec = 1; + break; + } + intarr[i] = strptr[i]; + i++; + } + + /* Assign length of integer part to intarr_len. */ + intarr_len = i; + intarr[i] = '\0'; + + if (no_dec) { + /* Currently needed only for single digit corepll ratios */ + mulconst=10; + decval = 0; + } else { + j = 0; + i++; /* Skipping the decimal point */ + while ((strptr[i] > 47) && (strptr[i] < 58)) { + decarr[j] = strptr[i]; + i++; + j++; + } + + decarr_len = j; + decarr[j] = '\0'; + + mulconst = 1; + for (i = 0; i < decarr_len; i++) + mulconst *= 10; + decval = simple_strtoul(decarr, NULL, 10); + } + + intval = simple_strtoul(intarr, NULL, 10); + intval = intval * mulconst; + + retval = intval + decval; + + return retval; +} diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h new file mode 100644 index 0000000..cd9a45d --- /dev/null +++ b/board/mpc8641hpcn/pixis.h @@ -0,0 +1,33 @@ +/* + * Copyright 2006 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int set_px_sysclk(ulong sysclk); +extern int set_px_mpxpll(ulong mpxpll); +extern int set_px_corepll(ulong corepll); +extern void read_from_px_regs(int set); +extern void read_from_px_regs_altbank(int set); +extern void set_altbank(void); +extern void set_px_go(void); +extern void set_px_go_with_watchdog(void); +extern int disable_watchdog(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]); +extern ulong strfractoint(uchar *strptr); -- cgit v1.1 From 4d3d729c16c392d2982d3266b659d333c927697d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:24:28 -0500 Subject: Moved mpc8641hpcn_board_reset() out of cpu/ into board/. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 93 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d02a7ef..dbc9b5e 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -25,6 +25,7 @@ */ #include +#include #include #include #include @@ -35,6 +36,9 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif +#include "pixis.h" + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -292,4 +296,93 @@ ft_board_setup(void *blob, bd_t *bd) #endif +void +mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + ulong val; + ulong corepll; + + if (argc > 1) { + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + + } else if(argv[2][1] == 'd'){ + /* Reset from next bank without changing frequencies but with watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* Reset from next bank without changing frequency and without watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Resetting board to boot from the other bank....\n"); + set_px_go(); + } + + default: + goto my_usage; + } + + my_usage: + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } else + out8(PIXIS_BASE+PIXIS_RST,0); +} -- cgit v1.1 From 3d5c5be547445dd3bd2eb7368d80df03ea437970 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:39:34 -0500 Subject: Removed unneeded local_bus_init() from 8641HPCN board. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index dbc9b5e..0b08df2 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -45,7 +45,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); extern long int spd_sdram(void); -void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); @@ -91,11 +90,6 @@ int checkboard (void) printf("PCI-EXPRESS1: Disabled\n"); #endif - /* - * Initialize local bus. - */ - local_bus_init(); - return 0; } @@ -129,34 +123,6 @@ initdram(int board_type) } -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; -} - #if defined(CFG_DRAM_TEST) int testdram(void) { -- cgit v1.1 From cb5965fb95b77a49f4e6af95248e0c849f4af03e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 12:44:44 -0500 Subject: White space cleanup. Some 80-column cleanups. Convert printf() to puts() where possible. Use #include "spd_sdram.h" as needed. Enhanced reset command usage message a bit. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 227 +++++++++++++++++++++------------------- 1 file changed, 117 insertions(+), 110 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 0b08df2..5cd3e97 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #include "pixis.h" - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif -extern long int spd_sdram(void); +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif void sdram_init(void); long int fixed_sdram(void); @@ -51,7 +52,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { - return 0; + return 0; } int checkboard (void) @@ -60,34 +61,32 @@ int checkboard (void) #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - - if ((io_sel==2 || io_sel==3 || io_sel==5 \ - || io_sel==6 || io_sel==7 || io_sel==0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - printf ("PCI-EXPRESS 1: Disabled\n"); - } + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } #else - printf("PCI-EXPRESS1: Disabled\n"); + puts("PCI-EXPRESS1: Disabled\n"); #endif return 0; @@ -98,7 +97,6 @@ long int initdram(int board_type) { long dram_size = 0; - extern long spd_sdram (void); #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); @@ -110,7 +108,7 @@ initdram(int board_type) puts(" DDR: "); return dram_size; #endif - + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. @@ -130,7 +128,7 @@ int testdram(void) uint *pend = (uint *) CFG_MEMTEST_END; uint *p; - printf("SDRAM test phase 1:\n"); + puts("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaaaaaa; @@ -141,7 +139,7 @@ int testdram(void) } } - printf("SDRAM test phase 2:\n"); + puts("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x55555555; @@ -152,7 +150,7 @@ int testdram(void) } } - printf("SDRAM test passed.\n"); + puts("SDRAM test passed.\n"); return 0; } #endif @@ -177,9 +175,9 @@ long int fixed_sdram(void) ddr->sdram_mode_1 = CFG_DDR_MODE_1; ddr->sdram_mode_2 = CFG_DDR_MODE_2; ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; #if defined (CONFIG_DDR_ECC) @@ -187,7 +185,7 @@ long int fixed_sdram(void) ddr->err_sbe = 0x00ff0000; #endif asm("sync;isync"); - + udelay(500); #if defined (CONFIG_DDR_ECC) @@ -198,7 +196,7 @@ long int fixed_sdram(void) ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; #endif asm("sync; isync"); - + udelay(500); #endif return CFG_SDRAM_SIZE * 1024 * 1024; @@ -251,13 +249,12 @@ ft_board_setup(void *blob, bd_t *bd) int len; ft_cpu_setup(blob, bd); - + p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } - } #endif @@ -269,86 +266,96 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong val; ulong corepll; - if (argc > 1) { - cmd = argv[1][1]; - switch (cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); + /* + * No args is a simple reset request. + */ + if (argv <= 0) { + out8(PIXIS_BASE + PIXIS_RST, 0); + /* not reached */ + } + + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; - val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + while (1); /* Not reached */ - corepll = strfractoint(argv[3]); + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); } else goto my_usage; - while (1); /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - - } else if(argv[2][1] == 'd'){ - /* Reset from next bank without changing frequencies but with watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - - } else { - /* Reset from next bank without changing frequency and without watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Resetting board to boot from the other bank....\n"); - set_px_go(); - } + while(1); /* Not reached */ - default: - goto my_usage; + } else if(argv[2][1] == 'd'){ + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* + * Reset from next bank without changing + * frequency and without watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank....\n"); + set_px_go(); } - my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; + default: + goto my_usage; + } - } else - out8(PIXIS_BASE+PIXIS_RST,0); + my_usage: + puts("\nUsage: reset cf \n"); + puts(" reset altbank [cf ]\n"); + puts(" reset altbank [wd]\n"); + puts("For example: reset cf 40 2.5 10\n"); + puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } -- cgit v1.1 From c934f655f9aeca70a5c5f88b465d9e9d57a8d22e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 13:55:35 -0500 Subject: Review cleanups. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/config.mk | 2 +- board/mpc8641hpcn/init.S | 26 ++++++++++++-------------- board/mpc8641hpcn/mpc8641hpcn.c | 4 ++-- board/mpc8641hpcn/u-boot.lds | 2 +- 4 files changed, 16 insertions(+), 18 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 4bdceec..989a40b 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -1,5 +1,5 @@ # Copyright 2004 Freescale Semiconductor. -# Modified by Jeff Brown (jeffrey@freescale.com) +# Modified by Jeff Brown # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 5f19fdf..69954a8 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -59,7 +59,6 @@ #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) /* @@ -72,7 +71,6 @@ #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) -/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) @@ -86,7 +84,7 @@ #define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) #endif - .section .bootpg, "ax" + .section .bootpg, "ax" .globl law_entry law_entry: lis r7,CFG_CCSRBAR@h @@ -110,8 +108,8 @@ law_entry: stwu r6, 0x20(r4) lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) /* LAWBAR3, LAWAR3 */ lis r6,LAWBAR3@h @@ -127,7 +125,7 @@ law_entry: ori r6,r6,LAWBAR4@l stwu r6, 0x20(r4) - lis r6,LAWAR4@h + lis r6,LAWAR4@h ori r6,r6,LAWAR4@l stwu r6, 0x20(r5) /* LAWBAR5, LAWAR5 */ @@ -157,14 +155,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) blr diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5cd3e97..c6b2a5b 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2002 Scott McNutt @@ -352,7 +352,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto my_usage; } - my_usage: +my_usage: puts("\nUsage: reset cf \n"); puts(" reset altbank [cf ]\n"); puts(" reset altbank [wd]\n"); diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index c5c40e7..b34de8e 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -1,7 +1,7 @@ /* * (C) Copyright 2004, Freescale, Inc. * (C) Copyright 2002,2003, Motorola,Inc. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * * See file CREDITS for list of people who contributed to this * project. -- cgit v1.1 From c83ae9ea6d93abbe751bf8a3396236a084e56f87 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 6 Jun 2006 16:54:29 -0400 Subject: Modify the IRQ of DUART2 --- board/mpc8641hpcn/oftree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 26ce661..a11c321 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <2a 3>; + interrupts = <1c 3>; interrupt-parent = <40000>; }; -- cgit v1.1 From d9bf4858fca5aa4d651b283270f77da72ebadfd5 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 7 Jun 2006 10:52:49 -0500 Subject: Allow DTC path to be passed in. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 2613730..060db84 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -31,8 +31,12 @@ SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) +ifndef DTC +DTC := dtc +endif + %.dtb: %.dts - dtc -f -V 0x10 -I dts -O dtb $< >$@ + $(DTC) -f -V 0x10 -I dts -O dtb $< >$@ %.c: %.dtb xxd -i $< \ -- cgit v1.1 From 8be429a5ddbf0ebe2d94174ba58fcfc7a24285dc Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Tue, 20 Jun 2006 17:47:15 +0800 Subject: Reworked IRQ mapping in OF-tree. --- board/mpc8641hpcn/oftree.dts | 94 ++++++++++++++++++++++++++------------------ 1 file changed, 55 insertions(+), 39 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index a11c321..32ba367 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -71,7 +71,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3000 100>; - interrupts = <2b 0>; + interrupts = <2b 2>; interrupt-parent = <40000>; dfsrr; }; @@ -80,7 +80,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3100 100>; - interrupts = <2b 0>; + interrupts = <2b 2>; interrupt-parent = <40000>; dfsrr; }; @@ -95,28 +95,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <3>; device_type = "ethernet-phy"; }; @@ -130,7 +130,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = <1d 3 1e 3 22 3>; + interrupts = <1d 2 1e 2 22 2>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -143,7 +143,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <23 3 24 3 28 3>; + interrupts = <23 2 24 2 28 2>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -156,7 +156,7 @@ compatible = "gianfar"; reg = <26000 1000>; address = [ 00 E0 0C 00 02 FD ]; - interrupts = <1F 3 20 3 21 3>; + interrupts = <1F 2 20 2 21 2>; interrupt-parent = <40000>; phy-handle = <2452002>; }; @@ -169,16 +169,16 @@ compatible = "gianfar"; reg = <27000 1000>; address = [ 00 E0 0C 00 03 FD ]; - interrupts = <25 3 26 3 27 3>; + interrupts = <25 2 26 2 27 2>; interrupt-parent = <40000>; phy-handle = <2452003>; }; serial@4500 { device_type = "serial"; - compatible = "ns16550"; + compatible = "ns16550"; reg = <4500 100>; clock-frequency = <0>; - interrupts = <2a 3>; + interrupts = <2a 2>; interrupt-parent = <40000>; }; @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <1c 3>; + interrupts = <2a 2>; interrupt-parent = <40000>; }; @@ -204,8 +204,8 @@ 01000000 0 00000000 e2000000 0 00100000>; clock-frequency = <1fca055>; interrupt-parent = <40000>; - interrupts = <8 0>; - interrupt-map-mask = ; + interrupts = <18 2>; + interrupt-map-mask = ; interrupt-map = < /* IDSEL 0x11 */ 8800 0 0 1 40000 3 0 @@ -220,16 +220,16 @@ 9000 0 0 4 40000 3 0 /* IDSEL 0x13 */ - 9800 0 0 1 40000 5 0 - 9800 0 0 2 40000 6 0 - 9800 0 0 3 40000 3 0 - 9800 0 0 4 40000 4 0 + 9800 0 0 1 40000 0 0 + 9800 0 0 2 40000 0 0 + 9800 0 0 3 40000 0 0 + 9800 0 0 4 40000 0 0 /* IDSEL 0x14 */ - a000 0 0 1 40000 6 0 - a000 0 0 2 40000 3 0 - a000 0 0 3 40000 4 0 - a000 0 0 4 40000 5 0 + a000 0 0 1 40000 0 0 + a000 0 0 2 40000 0 0 + a000 0 0 3 40000 0 0 + a000 0 0 4 40000 0 0 /* IDSEL 0x15 */ a800 0 0 1 40000 0 0 @@ -262,41 +262,41 @@ c800 0 0 4 40000 0 0 /* IDSEL 0x1a */ - d000 0 0 1 40000 0 0 - d000 0 0 2 40000 0 0 - d000 0 0 3 40000 0 0 - d000 0 0 4 40000 0 0 + d000 0 0 1 40000 6 0 + d000 0 0 2 40000 3 0 + d000 0 0 3 40000 4 0 + d000 0 0 4 40000 5 0 /* IDSEL 0x1b */ - d800 0 0 1 40000 0 0 + d800 0 0 1 40000 5 0 d800 0 0 2 40000 0 0 d800 0 0 3 40000 0 0 d800 0 0 4 40000 0 0 /* IDSEL 0x1c */ - e000 0 0 1 40000 0 0 - e000 0 0 2 40000 0 0 - e000 0 0 3 40000 0 0 - e000 0 0 4 40000 0 0 + e000 0 0 1 40000 9 0 + e000 0 0 2 40000 a 0 + e000 0 0 3 40000 c 0 + e000 0 0 4 40000 7 0 /* IDSEL 0x1d */ - e800 0 0 1 40000 0 0 - e800 0 0 2 40000 0 0 - e800 0 0 3 40000 0 0 + e800 0 0 1 40000 9 0 + e800 0 0 2 40000 a 0 + e800 0 0 3 40000 b 0 e800 0 0 4 40000 0 0 /* IDSEL 0x1e */ - f000 0 0 1 40000 0 0 + f000 0 0 1 40000 c 0 f000 0 0 2 40000 0 0 f000 0 0 3 40000 0 0 f000 0 0 4 40000 0 0 /* IDSEL 0x1f */ f800 0 0 1 40000 6 0 - f800 0 0 2 40000 6 0 - f800 0 0 3 40000 6 0 - f800 0 0 4 40000 6 0 + f800 0 0 2 40000 0 0 + f800 0 0 3 40000 0 0 + f800 0 0 4 40000 0 0 >; }; pic@40000 { @@ -310,6 +310,22 @@ compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; + interrupts = < + 10 2 11 2 12 2 13 2 + 14 2 15 2 16 2 17 2 + 18 2 19 2 1a 2 1b 2 + 1c 2 1d 2 1e 2 1f 2 + 20 2 21 2 22 2 23 2 + 24 2 25 2 26 2 27 2 + 28 2 29 2 2a 2 2b 2 + 2c 2 2d 2 2e 2 2f 2 + 30 2 31 2 32 2 33 2 + 34 2 35 2 36 2 37 2 + 38 2 39 2 2a 2 3b 2 + 3c 2 3d 2 3e 2 3f 2 + 48 1 49 2 4a 1 + >; + interrupt-parent = <40000>; }; }; }; -- cgit v1.1 From 684623ce92c5fd32e7db2d6e016945a67c5ffaba Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 22 Jun 2006 08:51:46 -0500 Subject: Fix bug in 8641hpcn reset command with no args. Signed-off-by: Haiying Wang Acked-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index c6b2a5b..2626ccc 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -269,7 +269,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * No args is a simple reset request. */ - if (argv <= 0) { + if (argc <= 1) { out8(PIXIS_BASE + PIXIS_RST, 0); /* not reached */ } -- cgit v1.1 From bea3f28d285942bf3f7ab339ce85178ded544225 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 12 Jul 2006 10:48:05 -0400 Subject: Add support for reading and writing mac addresses to or from ID EEPROM. Added code for reading and writing Mac addresses to/from ID EEPROM(0x57). With attached patch, we can use command "mac/mac read/mac save/" to read and write EEPROM under u-boot prompt. U-boot will calculate the checksum of EEPROM while bootup, if it is right, then u-boot will check whether the mac address of eTSEC0/1/2/3 is availalbe (non-zero). If there is mac address availabe in EEPROM, u-boot will use it, otherewise, u-boot will use the mac address defined in MPC8641HPCN.h. This matches the requirement to set unique mac address for each TSEC port. Signed-off-by: Haiying Wang Signed-off-by: York Sun --- board/mpc8641hpcn/Makefile | 2 +- board/mpc8641hpcn/sys_eeprom.c | 244 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 board/mpc8641hpcn/sys_eeprom.c (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 060db84..0ebed87 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o pixis.o oftree.o +OBJS := $(BOARD).o pixis.o sys_eeprom.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c new file mode 100644 index 0000000..733a57f --- /dev/null +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -0,0 +1,244 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CFG_ID_EEPROM +typedef struct { + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5];/* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37];/* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6];/* 0x0042 - 0x0071 */ + unsigned char res_2[126];/* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ +} EEPROM_data; + +static EEPROM_data mac_data; + +int mac_show(void) +{ + int i; + unsigned char ethaddr[8][18]; + + printf("ID %c%c%c%c\n", mac_data.id[0],\ + mac_data.id[1],\ + mac_data.id[2],\ + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ + mac_data.errata[1],\ + mac_data.errata[2],\ + mac_data.errata[3],\ + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ + mac_data.date[1],\ + mac_data.date[2],\ + mac_data.date[3],\ + mac_data.date[4],\ + mac_data.date[5],\ + mac_data.date[6]); + for (i = 0; i < 8; i++) { + sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ + mac_data.mac[i][0],\ + mac_data.mac[i][1],\ + mac_data.mac[i][2],\ + mac_data.mac[i][3],\ + mac_data.mac[i][4],\ + mac_data.mac[i][5]); + printf("MAC %d %s\n", i, ethaddr[i]); + } + + setenv("ethaddr", ethaddr[0]); + setenv("eth1addr", ethaddr[1]); + setenv("eth2addr", ethaddr[2]); + setenv("eth3addr", ethaddr[3]); + + return 0; +} + +int mac_read(void) +{ + int ret,length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *data; + + length = sizeof(EEPROM_data); + ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); + if (ret) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + printf("Check CRC on reading ..."); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + return -1; + } + else { + printf("CRC OK\n"); + mac_show(); + } + return 0; +} + +int mac_prog(void) +{ + int ret, i, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR,*ptr; + unsigned char * eeprom_data = (unsigned char *)(&mac_data); + + for (i = 0; i < sizeof(mac_data.res_1); i++) + mac_data.res_1[i] = 0; + for (i = 0;i < sizeof(mac_data.res_2); i++) + mac_data.res_2[i] = 0; + length = sizeof(EEPROM_data); + crc = crc32 (crc, eeprom_data, length-4); + mac_data.crc = crc; + for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { + ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); + udelay(5000); /* 5ms write cycle timing */ + if (ret) + break; + } + if (ret) { + printf("Programming failed.\n"); + return -1; + } + else { + printf("Programming %d bytes. Reading back ...\n",length); + mac_read(); + } + return 0; +} + +int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char cmd = 's'; + unsigned long long mac_val; + + if(i2c_probe(ID_EEPROM_ADDR) != 0) + return -1; + + if(argc>1) { + cmd = argv[1][0]; + switch (cmd) { + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i=0; i<4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i=0; i<12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i=0; i<5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i=0; i<7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2],NULL,16); + for (i=0; i<6; i++) { + mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); + } + break; + case 'h': /* help */ + default: + printf ("Usage:\n%s\n", cmdtp->usage); + break; + } + } + else { + mac_show(); + } + return 0; +} + +int mac_read_from_eeprom(void) +{ + int length,i; + unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + unsigned int crc = 0; + + length = sizeof(EEPROM_data); + if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + return -1; + } + else { + for(i=0; i<4; i++) { + if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ + mac_data.mac[i][0], \ + mac_data.mac[i][1], \ + mac_data.mac[i][2], \ + mac_data.mac[i][3], \ + mac_data.mac[i][4], \ + mac_data.mac[i][5]); + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + setenv(enetvar, ethaddr[i]); + } + } + } + return 0; +} +#endif /* CFG_ID_EEPROM */ -- cgit v1.1 From c86360b830f1eecd7a72208575dde4f57879faea Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Fri, 28 Jul 2006 00:01:34 +0800 Subject: Fixed OF device tree of mpc86xxhpcn board. The changes works in with kernel irq mapping rework. Signed-off-by: Zhang Wei --- board/mpc8641hpcn/oftree.dts | 136 ++++++++++++++++++++++++------------------- 1 file changed, 75 insertions(+), 61 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 32ba367..e3f5efa 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -205,99 +205,113 @@ clock-frequency = <1fca055>; interrupt-parent = <40000>; interrupts = <18 2>; - interrupt-map-mask = ; + interrupt-map-mask = ; interrupt-map = < /* IDSEL 0x11 */ - 8800 0 0 1 40000 3 0 - 8800 0 0 2 40000 4 0 - 8800 0 0 3 40000 5 0 - 8800 0 0 4 40000 6 0 + 8800 0 0 1 4d0 3 2 + 8800 0 0 2 4d0 4 2 + 8800 0 0 3 4d0 5 2 + 8800 0 0 4 4d0 6 2 /* IDSEL 0x12 */ - 9000 0 0 1 40000 4 0 - 9000 0 0 2 40000 5 0 - 9000 0 0 3 40000 6 0 - 9000 0 0 4 40000 3 0 + 9000 0 0 1 4d0 4 2 + 9000 0 0 2 4d0 5 2 + 9000 0 0 3 4d0 6 2 + 9000 0 0 4 4d0 3 2 /* IDSEL 0x13 */ - 9800 0 0 1 40000 0 0 - 9800 0 0 2 40000 0 0 - 9800 0 0 3 40000 0 0 - 9800 0 0 4 40000 0 0 + 9800 0 0 1 4d0 0 0 + 9800 0 0 2 4d0 0 0 + 9800 0 0 3 4d0 0 0 + 9800 0 0 4 4d0 0 0 /* IDSEL 0x14 */ - a000 0 0 1 40000 0 0 - a000 0 0 2 40000 0 0 - a000 0 0 3 40000 0 0 - a000 0 0 4 40000 0 0 + a000 0 0 1 4d0 0 0 + a000 0 0 2 4d0 0 0 + a000 0 0 3 4d0 0 0 + a000 0 0 4 4d0 0 0 /* IDSEL 0x15 */ - a800 0 0 1 40000 0 0 - a800 0 0 2 40000 0 0 - a800 0 0 3 40000 0 0 - a800 0 0 4 40000 0 0 + a800 0 0 1 4d0 0 0 + a800 0 0 2 4d0 0 0 + a800 0 0 3 4d0 0 0 + a800 0 0 4 4d0 0 0 /* IDSEL 0x16 */ - b000 0 0 1 40000 0 0 - b000 0 0 2 40000 0 0 - b000 0 0 3 40000 0 0 - b000 0 0 4 40000 0 0 + b000 0 0 1 4d0 0 0 + b000 0 0 2 4d0 0 0 + b000 0 0 3 4d0 0 0 + b000 0 0 4 4d0 0 0 /* IDSEL 0x17 */ - b800 0 0 1 40000 0 0 - b800 0 0 2 40000 0 0 - b800 0 0 3 40000 0 0 - b800 0 0 4 40000 0 0 + b800 0 0 1 4d0 0 0 + b800 0 0 2 4d0 0 0 + b800 0 0 3 4d0 0 0 + b800 0 0 4 4d0 0 0 /* IDSEL 0x18 */ - c000 0 0 1 40000 0 0 - c000 0 0 2 40000 0 0 - c000 0 0 3 40000 0 0 - c000 0 0 4 40000 0 0 + c000 0 0 1 4d0 0 0 + c000 0 0 2 4d0 0 0 + c000 0 0 3 4d0 0 0 + c000 0 0 4 4d0 0 0 /* IDSEL 0x19 */ - c800 0 0 1 40000 0 0 - c800 0 0 2 40000 0 0 - c800 0 0 3 40000 0 0 - c800 0 0 4 40000 0 0 + c800 0 0 1 4d0 0 0 + c800 0 0 2 4d0 0 0 + c800 0 0 3 4d0 0 0 + c800 0 0 4 4d0 0 0 /* IDSEL 0x1a */ - d000 0 0 1 40000 6 0 - d000 0 0 2 40000 3 0 - d000 0 0 3 40000 4 0 - d000 0 0 4 40000 5 0 + d000 0 0 1 4d0 6 2 + d000 0 0 2 4d0 3 2 + d000 0 0 3 4d0 4 2 + d000 0 0 4 4d0 5 2 /* IDSEL 0x1b */ - d800 0 0 1 40000 5 0 - d800 0 0 2 40000 0 0 - d800 0 0 3 40000 0 0 - d800 0 0 4 40000 0 0 + d800 0 0 1 4d0 5 2 + d800 0 0 2 4d0 0 0 + d800 0 0 3 4d0 0 0 + d800 0 0 4 4d0 0 0 /* IDSEL 0x1c */ - e000 0 0 1 40000 9 0 - e000 0 0 2 40000 a 0 - e000 0 0 3 40000 c 0 - e000 0 0 4 40000 7 0 + e000 0 0 1 4d0 9 2 + e000 0 0 2 4d0 a 2 + e000 0 0 3 4d0 c 2 + e000 0 0 4 4d0 7 2 /* IDSEL 0x1d */ - e800 0 0 1 40000 9 0 - e800 0 0 2 40000 a 0 - e800 0 0 3 40000 b 0 - e800 0 0 4 40000 0 0 + e800 0 0 1 4d0 9 2 + e800 0 0 2 4d0 a 2 + e800 0 0 3 4d0 b 2 + e800 0 0 4 4d0 0 0 /* IDSEL 0x1e */ - f000 0 0 1 40000 c 0 - f000 0 0 2 40000 0 0 - f000 0 0 3 40000 0 0 - f000 0 0 4 40000 0 0 + f000 0 0 1 4d0 c 2 + f000 0 0 2 4d0 0 0 + f000 0 0 3 4d0 0 0 + f000 0 0 4 4d0 0 0 /* IDSEL 0x1f */ - f800 0 0 1 40000 6 0 - f800 0 0 2 40000 0 0 - f800 0 0 3 40000 0 0 - f800 0 0 4 40000 0 0 + f800 0 0 1 4d0 6 2 + f800 0 0 2 4d0 0 0 + f800 0 0 3 4d0 0 0 + f800 0 0 4 4d0 0 0 >; + i8259@4d0 { + linux,phandle = <4d0>; + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + big-endian; + interrupts = <49 2>; + interrupt-parent = <40000>; + }; + }; pic@40000 { linux,phandle = <40000>; -- cgit v1.1 From 239db37c94f7a92941c4465feceb867c609241c5 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:18 -0400 Subject: Move get_board_sys_clk to board directory --- board/mpc8641hpcn/mpc8641hpcn.c | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 2626ccc..5023c1c 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -359,3 +359,67 @@ my_usage: puts("For example: reset cf 40 2.5 10\n"); puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} + -- cgit v1.1 From 71748af833ca1017edf1415be376366ff2937d17 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:35 -0400 Subject: Correct the irq value of DUART2 --- board/mpc8641hpcn/oftree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index e3f5efa..742a140 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <1c 2>; interrupt-parent = <40000>; }; -- cgit v1.1 From 8fc8bd2cc479b6cd188fdede4010e0e052970b8a Mon Sep 17 00:00:00 2001 From: John Traill Date: Wed, 9 Aug 2006 14:33:50 +0100 Subject: Add Rapidio support for the MPC8641HPCN Signed-off-by: John Traill --- board/mpc8641hpcn/init.S | 12 ++++++++++++ board/mpc8641hpcn/oftree.dts | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 69954a8..c6ea55e 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -84,6 +84,9 @@ #define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) #endif +#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .section .bootpg, "ax" .globl law_entry law_entry: @@ -164,5 +167,14 @@ law_entry: ori r6,r6,LAWAR8@l stwu r6, 0x20(r5) + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + blr diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 742a140..99d75ca 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -341,6 +341,48 @@ >; interrupt-parent = <40000>; }; + rio@c0000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "rio"; + model = "pq38"; + compatible = "85xx"; + ranges = <0 c0000000 20000000>; + reg = ; + linux,phandle = ; + }; + rio_message@d3000 { + device_type = "network"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <35 2 36 2>; + interrupt-parent = <40000>; + }; + rio_message@d3100 { + device_type = "network"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <37 2 38 2>; + interrupt-parent = <40000>; + }; + rio_doorbell@d3400 { + device_type = "doorbell"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <31 2 32 2>; + interrupt-parent = <40000>; + }; + rio_portwrite@d34e0 { + device_type = "portwrite"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <30 2>; + interrupt-parent = <40000>; + }; }; }; -- cgit v1.1 From 40bc83559db5745681909fd7382ae509567e116d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 9 Aug 2006 15:32:16 -0500 Subject: Removed MPC8641HPCN DTS source file from build. It is no longer linked into U-Boot; its sources are now located in the kernel tree. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 18 +- board/mpc8641hpcn/oftree.dts | 388 ------------------------------------------- 2 files changed, 3 insertions(+), 403 deletions(-) delete mode 100644 board/mpc8641hpcn/oftree.dts (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 0ebed87..f70f44b 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,27 +25,15 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o pixis.o sys_eeprom.o oftree.o +OBJS := $(BOARD).o pixis.o sys_eeprom.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) -ifndef DTC -DTC := dtc -endif - -%.dtb: %.dts - $(DTC) -f -V 0x10 -I dts -O dtb $< >$@ - -%.c: %.dtb - xxd -i $< \ - | sed -e "s/^unsigned char/const unsigned char/g" \ - | sed -e "s/^unsigned int/const unsigned int/g" > $@ - - clean: - rm -f $(OBJS) $(SOBJS) *.dtb oftree.c + rm -f $(OBJS) $(SOBJS) + .PHONY: distclean distclean: clean rm -f $(LIB) core *.bak .depend diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts deleted file mode 100644 index 99d75ca..0000000 --- a/board/mpc8641hpcn/oftree.dts +++ /dev/null @@ -1,388 +0,0 @@ -/* - * MPC8641 HPCN Device Tree Source - * - * Copyright 2006 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - - -/ { - model = "MPC8641HPCN"; - compatible = "mpc86xx"; - #address-cells = <1>; - #size-cells = <1>; - linux,phandle = <100>; - - cpus { - #cpus = <2>; - #address-cells = <1>; - #size-cells = <0>; - linux,phandle = <200>; - - PowerPC,8641@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // From uboot - clock-frequency = <0>; // From uboot - 32-bit; - linux,phandle = <201>; - linux,boot-cpu; - }; - PowerPC,8641@1 { - device_type = "cpu"; - reg = <1>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // From uboot - clock-frequency = <0>; // From uboot - 32-bit; - linux,phandle = <202>; - }; - }; - - memory { - device_type = "memory"; - linux,phandle = <300>; - reg = <00000000 40000000>; // 1G at 0x0 - }; - - soc8641@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - device_type = "soc"; - ranges = <0 f8000000 00100000>; - reg = ; // CCSRBAR 1M - bus-frequency = <0>; - - i2c@3000 { - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; - interrupt-parent = <40000>; - dfsrr; - }; - - i2c@3100 { - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; - interrupt-parent = <40000>; - dfsrr; - }; - - mdio@24520 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "mdio"; - compatible = "gianfar"; - reg = <24520 20>; - linux,phandle = <24520>; - ethernet-phy@0 { - linux,phandle = <2452000>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <0>; - device_type = "ethernet-phy"; - }; - ethernet-phy@1 { - linux,phandle = <2452001>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <1>; - device_type = "ethernet-phy"; - }; - ethernet-phy@2 { - linux,phandle = <2452002>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <2>; - device_type = "ethernet-phy"; - }; - ethernet-phy@3 { - linux,phandle = <2452003>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <3>; - device_type = "ethernet-phy"; - }; - }; - - ethernet@24000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <24000 1000>; - address = [ 00 E0 0C 00 73 00 ]; - interrupts = <1d 2 1e 2 22 2>; - interrupt-parent = <40000>; - phy-handle = <2452000>; - }; - - ethernet@25000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <25000 1000>; - address = [ 00 E0 0C 00 73 01 ]; - interrupts = <23 2 24 2 28 2>; - interrupt-parent = <40000>; - phy-handle = <2452001>; - }; - - ethernet@26000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <26000 1000>; - address = [ 00 E0 0C 00 02 FD ]; - interrupts = <1F 2 20 2 21 2>; - interrupt-parent = <40000>; - phy-handle = <2452002>; - }; - - ethernet@27000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <27000 1000>; - address = [ 00 E0 0C 00 03 FD ]; - interrupts = <25 2 26 2 27 2>; - interrupt-parent = <40000>; - phy-handle = <2452003>; - }; - serial@4500 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4500 100>; - clock-frequency = <0>; - interrupts = <2a 2>; - interrupt-parent = <40000>; - }; - - serial@4600 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4600 100>; - clock-frequency = <0>; - interrupts = <1c 2>; - interrupt-parent = <40000>; - }; - - pci@8000 { - compatible = "86xx"; - device_type = "pci"; - linux,phandle = <8000>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - bus-range = <0 fe>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <1fca055>; - interrupt-parent = <40000>; - interrupts = <18 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x11 */ - 8800 0 0 1 4d0 3 2 - 8800 0 0 2 4d0 4 2 - 8800 0 0 3 4d0 5 2 - 8800 0 0 4 4d0 6 2 - - /* IDSEL 0x12 */ - 9000 0 0 1 4d0 4 2 - 9000 0 0 2 4d0 5 2 - 9000 0 0 3 4d0 6 2 - 9000 0 0 4 4d0 3 2 - - /* IDSEL 0x13 */ - 9800 0 0 1 4d0 0 0 - 9800 0 0 2 4d0 0 0 - 9800 0 0 3 4d0 0 0 - 9800 0 0 4 4d0 0 0 - - /* IDSEL 0x14 */ - a000 0 0 1 4d0 0 0 - a000 0 0 2 4d0 0 0 - a000 0 0 3 4d0 0 0 - a000 0 0 4 4d0 0 0 - - /* IDSEL 0x15 */ - a800 0 0 1 4d0 0 0 - a800 0 0 2 4d0 0 0 - a800 0 0 3 4d0 0 0 - a800 0 0 4 4d0 0 0 - - /* IDSEL 0x16 */ - b000 0 0 1 4d0 0 0 - b000 0 0 2 4d0 0 0 - b000 0 0 3 4d0 0 0 - b000 0 0 4 4d0 0 0 - - /* IDSEL 0x17 */ - b800 0 0 1 4d0 0 0 - b800 0 0 2 4d0 0 0 - b800 0 0 3 4d0 0 0 - b800 0 0 4 4d0 0 0 - - /* IDSEL 0x18 */ - c000 0 0 1 4d0 0 0 - c000 0 0 2 4d0 0 0 - c000 0 0 3 4d0 0 0 - c000 0 0 4 4d0 0 0 - - /* IDSEL 0x19 */ - c800 0 0 1 4d0 0 0 - c800 0 0 2 4d0 0 0 - c800 0 0 3 4d0 0 0 - c800 0 0 4 4d0 0 0 - - /* IDSEL 0x1a */ - d000 0 0 1 4d0 6 2 - d000 0 0 2 4d0 3 2 - d000 0 0 3 4d0 4 2 - d000 0 0 4 4d0 5 2 - - - /* IDSEL 0x1b */ - d800 0 0 1 4d0 5 2 - d800 0 0 2 4d0 0 0 - d800 0 0 3 4d0 0 0 - d800 0 0 4 4d0 0 0 - - /* IDSEL 0x1c */ - e000 0 0 1 4d0 9 2 - e000 0 0 2 4d0 a 2 - e000 0 0 3 4d0 c 2 - e000 0 0 4 4d0 7 2 - - /* IDSEL 0x1d */ - e800 0 0 1 4d0 9 2 - e800 0 0 2 4d0 a 2 - e800 0 0 3 4d0 b 2 - e800 0 0 4 4d0 0 0 - - /* IDSEL 0x1e */ - f000 0 0 1 4d0 c 2 - f000 0 0 2 4d0 0 0 - f000 0 0 3 4d0 0 0 - f000 0 0 4 4d0 0 0 - - /* IDSEL 0x1f */ - f800 0 0 1 4d0 6 2 - f800 0 0 2 4d0 0 0 - f800 0 0 3 4d0 0 0 - f800 0 0 4 4d0 0 0 - >; - i8259@4d0 { - linux,phandle = <4d0>; - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <49 2>; - interrupt-parent = <40000>; - }; - - }; - pic@40000 { - linux,phandle = <40000>; - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; - interrupts = < - 10 2 11 2 12 2 13 2 - 14 2 15 2 16 2 17 2 - 18 2 19 2 1a 2 1b 2 - 1c 2 1d 2 1e 2 1f 2 - 20 2 21 2 22 2 23 2 - 24 2 25 2 26 2 27 2 - 28 2 29 2 2a 2 2b 2 - 2c 2 2d 2 2e 2 2f 2 - 30 2 31 2 32 2 33 2 - 34 2 35 2 36 2 37 2 - 38 2 39 2 2a 2 3b 2 - 3c 2 3d 2 3e 2 3f 2 - 48 1 49 2 4a 1 - >; - interrupt-parent = <40000>; - }; - rio@c0000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "rio"; - model = "pq38"; - compatible = "85xx"; - ranges = <0 c0000000 20000000>; - reg = ; - linux,phandle = ; - }; - rio_message@d3000 { - device_type = "network"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <35 2 36 2>; - interrupt-parent = <40000>; - }; - rio_message@d3100 { - device_type = "network"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <37 2 38 2>; - interrupt-parent = <40000>; - }; - rio_doorbell@d3400 { - device_type = "doorbell"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <31 2 32 2>; - interrupt-parent = <40000>; - }; - rio_portwrite@d34e0 { - device_type = "portwrite"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <30 2>; - interrupt-parent = <40000>; - }; - }; -}; - -- cgit v1.1 From 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 12:25:27 -0500 Subject: General indent and whitespace cleanups. --- board/mpc8641hpcn/mpc8641hpcn.c | 69 ++++++------ board/mpc8641hpcn/pixis.c | 21 ++-- board/mpc8641hpcn/sys_eeprom.c | 240 +++++++++++++++++++++------------------- 3 files changed, 170 insertions(+), 160 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5023c1c..b2cf4a9 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -50,12 +50,12 @@ void sdram_init(void); long int fixed_sdram(void); -int board_early_init_f (void) +int board_early_init_f(void) { return 0; } -int checkboard (void) +int checkboard(void) { puts("Board: MPC8641HPCN\n"); @@ -68,7 +68,7 @@ int checkboard (void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) @@ -80,7 +80,7 @@ int checkboard (void) debug(" with errors. Clearing. Now 0x%08x", pex1->pme_msg_det); } - debug ("\n"); + debug("\n"); } else { puts("PCI-EXPRESS 1: Disabled\n"); } @@ -99,9 +99,9 @@ initdram(int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = spd_sdram(); #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif #if defined(CFG_RAMBOOT) @@ -122,7 +122,8 @@ initdram(int board_type) #if defined(CFG_DRAM_TEST) -int testdram(void) +int +testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -134,7 +135,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -145,7 +146,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -160,11 +161,12 @@ int testdram(void) /* * Fixed sdram init -- doesn't use serial presence detect. */ -long int fixed_sdram(void) +long int +fixed_sdram(void) { #if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -211,28 +213,25 @@ long int fixed_sdram(void) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_fsl86xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} }; #endif static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP - config_table: pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table, #endif }; -#endif /* CONFIG_PCI */ - +#endif /* CONFIG_PCI */ -void -pci_init_board(void) +void pci_init_board(void) { #ifdef CONFIG_PCI extern void pci_mpc86xx_init(struct pci_controller *hose); @@ -260,7 +259,7 @@ ft_board_setup(void *blob, bd_t *bd) void -mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { char cmd; ulong val; @@ -276,7 +275,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cmd = argv[1][1]; switch (cmd) { - case 'f': /* reset with frequency changed */ + case 'f': /* reset with frequency changed */ if (argc < 5) goto my_usage; read_from_px_regs(0); @@ -294,7 +293,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while (1); /* Not reached */ + while (1) ; /* Not reached */ case 'l': if (argv[2][1] == 'f') { @@ -305,7 +304,8 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], + NULL, 10)); if (val == 3) { puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); set_altbank(); @@ -316,9 +316,9 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while(1); /* Not reached */ + while (1) ; /* Not reached */ - } else if(argv[2][1] == 'd'){ + } else if (argv[2][1] == 'd') { /* * Reset from alternate bank without changing * frequencies but with watchdog timer enabled. @@ -330,7 +330,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) read_from_px_regs_altbank(1); puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); set_px_go_with_watchdog(); - while(1); /* Not reached */ + while (1) ; /* Not reached */ } else { /* @@ -339,7 +339,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ read_from_px_regs(0); read_from_px_regs_altbank(0); - if(argc > 2) + if (argc > 2) goto my_usage; puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); set_altbank(); @@ -360,12 +360,14 @@ my_usage: puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + /* * get_board_sys_clk * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ */ -unsigned long get_board_sys_clk(ulong dummy) +unsigned long +get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; @@ -422,4 +424,3 @@ unsigned long get_board_sys_clk(ulong dummy) return val; } - diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c index f226b3e..964a17c 100644 --- a/board/mpc8641hpcn/pixis.c +++ b/board/mpc8641hpcn/pixis.c @@ -92,13 +92,13 @@ int set_px_sysclk(ulong sysclk) return 0; } - vclkh = (sysclk_s << 5) | sysclk_r ; + vclkh = (sysclk_s << 5) | sysclk_r; vclkl = sysclk_v; out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); - out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux); return 1; } @@ -118,7 +118,7 @@ int set_px_mpxpll(ulong mpxpll) case 12: case 14: case 16: - val = (u8)mpxpll; + val = (u8) mpxpll; break; default: printf("Unsupported MPXPLL ratio.\n"); @@ -245,19 +245,16 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* setting VCTL[WDEN] to 0 to disable watch dog */ tmp = in8(PIXIS_BASE + PIXIS_VCTL); - tmp &= ~ 0x08; + tmp &= ~0x08; out8(PIXIS_BASE + PIXIS_VCTL, tmp); return 0; } - U_BOOT_CMD( - diswd, 1, 0, disable_watchdog, - "diswd - Disable watchdog timer \n", - NULL -); - + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL); /* * This function takes the non-integral cpu:mpx pll ratio @@ -295,11 +292,11 @@ ulong strfractoint(uchar *strptr) if (no_dec) { /* Currently needed only for single digit corepll ratios */ - mulconst=10; + mulconst = 10; decval = 0; } else { j = 0; - i++; /* Skipping the decimal point */ + i++; /* Skipping the decimal point */ while ((strptr[i] > 47) && (strptr[i] < 58)) { decarr[j] = strptr[i]; i++; diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c index 733a57f..74e2a3d 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -29,16 +29,16 @@ #ifdef CFG_ID_EEPROM typedef struct { - unsigned char id[4]; /* 0x0000 - 0x0003 */ - unsigned char sn[12]; /* 0x0004 - 0x000F */ - unsigned char errata[5];/* 0x0010 - 0x0014 */ - unsigned char date[7]; /* 0x0015 - 0x001a */ - unsigned char res_1[37];/* 0x001b - 0x003f */ - unsigned char tab_size; /* 0x0040 */ - unsigned char tab_flag; /* 0x0041 */ - unsigned char mac[8][6];/* 0x0042 - 0x0071 */ - unsigned char res_2[126];/* 0x0072 - 0x00ef */ - unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5]; /* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37]; /* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ + unsigned char res_2[126]; /* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ } EEPROM_data; static EEPROM_data mac_data; @@ -48,30 +48,34 @@ int mac_show(void) int i; unsigned char ethaddr[8][18]; - printf("ID %c%c%c%c\n", mac_data.id[0],\ - mac_data.id[1],\ - mac_data.id[2],\ - mac_data.id[3]); - printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ - mac_data.errata[1],\ - mac_data.errata[2],\ - mac_data.errata[3],\ - mac_data.errata[4]); - printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ - mac_data.date[1],\ - mac_data.date[2],\ - mac_data.date[3],\ - mac_data.date[4],\ - mac_data.date[5],\ - mac_data.date[6]); + printf("ID %c%c%c%c\n", + mac_data.id[0], + mac_data.id[1], + mac_data.id[2], + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", + mac_data.errata[0], + mac_data.errata[1], + mac_data.errata[2], + mac_data.errata[3], + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", + mac_data.date[0], + mac_data.date[1], + mac_data.date[2], + mac_data.date[3], + mac_data.date[4], + mac_data.date[5], + mac_data.date[6]); for (i = 0; i < 8; i++) { - sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ - mac_data.mac[i][0],\ - mac_data.mac[i][1],\ - mac_data.mac[i][2],\ - mac_data.mac[i][3],\ - mac_data.mac[i][4],\ - mac_data.mac[i][5]); + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); printf("MAC %d %s\n", i, ethaddr[i]); } @@ -85,7 +89,7 @@ int mac_show(void) int mac_read(void) { - int ret,length; + int ret, length; unsigned int crc = 0; unsigned char dev = ID_EEPROM_ADDR, *data; @@ -98,12 +102,12 @@ int mac_read(void) data = (unsigned char *)(&mac_data); printf("Check CRC on reading ..."); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { - printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", + mac_data.crc, crc); return -1; - } - else { + } else { printf("CRC OK\n"); mac_show(); } @@ -114,94 +118,97 @@ int mac_prog(void) { int ret, i, length; unsigned int crc = 0; - unsigned char dev = ID_EEPROM_ADDR,*ptr; - unsigned char * eeprom_data = (unsigned char *)(&mac_data); + unsigned char dev = ID_EEPROM_ADDR, *ptr; + unsigned char *eeprom_data = (unsigned char *)(&mac_data); for (i = 0; i < sizeof(mac_data.res_1); i++) mac_data.res_1[i] = 0; - for (i = 0;i < sizeof(mac_data.res_2); i++) + for (i = 0; i < sizeof(mac_data.res_2); i++) mac_data.res_2[i] = 0; length = sizeof(EEPROM_data); - crc = crc32 (crc, eeprom_data, length-4); + crc = crc32(crc, eeprom_data, length - 4); mac_data.crc = crc; for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { - ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); - udelay(5000); /* 5ms write cycle timing */ + ret = + i2c_write(dev, i, 1, ptr, + (length - i) < 8 ? (length - i) : 8); + udelay(5000); /* 5ms write cycle timing */ if (ret) break; } if (ret) { printf("Programming failed.\n"); return -1; - } - else { - printf("Programming %d bytes. Reading back ...\n",length); + } else { + printf("Programming %d bytes. Reading back ...\n", length); mac_read(); } return 0; } -int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; char cmd = 's'; unsigned long long mac_val; - if(i2c_probe(ID_EEPROM_ADDR) != 0) + if (i2c_probe(ID_EEPROM_ADDR) != 0) return -1; - if(argc>1) { + if (argc > 1) { cmd = argv[1][0]; switch (cmd) { - case 'r': /* display */ - mac_read(); - break; - case 's': /* save */ - mac_prog(); - break; - case 'i': /* id */ - for (i=0; i<4; i++) { - mac_data.id[i] = argv[2][i]; - } - break; - case 'n': /* serial number */ - for (i=0; i<12; i++) { - mac_data.sn[i] = argv[2][i]; - } - break; - case 'e': /* errata */ - for (i=0; i<5; i++) { - mac_data.errata[i] = argv[2][i]; - } - break; - case 'd': /* date */ - for (i=0; i<7; i++) { - mac_data.date[i] = argv[2][i]; - } - break; - case 'p': /* number of ports */ - mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); - break; - case '0': /* mac 0 */ - case '1': /* mac 1 */ - case '2': /* mac 2 */ - case '3': /* mac 3 */ - case '4': /* mac 4 */ - case '5': /* mac 5 */ - case '6': /* mac 6 */ - case '7': /* mac 7 */ - mac_val = simple_strtoull(argv[2],NULL,16); - for (i=0; i<6; i++) { - mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); - } - break; - case 'h': /* help */ - default: - printf ("Usage:\n%s\n", cmdtp->usage); - break; + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i = 0; i < 4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i = 0; i < 12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i = 0; i < 5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i = 0; i < 7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = + (unsigned char)simple_strtoul(argv[2], NULL, 16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2], NULL, 16); + for (i = 0; i < 6; i++) { + mac_data.mac[cmd - '0'][i] = + *((unsigned char *) + (((unsigned int)(&mac_val)) + i + 2)); + } + break; + case 'h': /* help */ + default: + printf("Usage:\n%s\n", cmdtp->usage); + break; } - } - else { + } else { mac_show(); } return 0; @@ -209,36 +216,41 @@ int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int mac_read_from_eeprom(void) { - int length,i; - unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + int length, i; + unsigned char dev = ID_EEPROM_ADDR; + unsigned char *data; + unsigned char ethaddr[4][18]; + unsigned char enetvar[32]; unsigned int crc = 0; length = sizeof(EEPROM_data); - if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { printf("Read failed.\n"); return -1; } data = (unsigned char *)(&mac_data); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { return -1; - } - else { - for(i=0; i<4; i++) { - if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ - mac_data.mac[i][0], \ - mac_data.mac[i][1], \ - mac_data.mac[i][2], \ - mac_data.mac[i][3], \ - mac_data.mac[i][4], \ + } else { + for (i = 0; i < 4; i++) { + if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], mac_data.mac[i][5]); - sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + sprintf(enetvar, + i ? "eth%daddr" : "ethaddr", + i); setenv(enetvar, ethaddr[i]); } } } return 0; } -#endif /* CFG_ID_EEPROM */ +#endif /* CFG_ID_EEPROM */ -- cgit v1.1 From afbdc649f8751e4f4f1a6f527edfe139773f2c15 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 19 Sep 2006 09:34:10 -0500 Subject: Modified makefile for new build mechanism. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index f70f44b..46214ed 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -23,12 +23,16 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := $(BOARD).o pixis.o sys_eeprom.o +COBJS := $(BOARD).o pixis.o sys_eeprom.o SOBJS := init.o -$(LIB): $(OBJS) $(SOBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) clean: @@ -40,10 +44,9 @@ distclean: clean ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -ifeq ($(filter distclean, $(MAKECMDGOALS)),) --include .depend -endif +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend ######################################################################### -- cgit v1.1 From 7b382b7125f2397cce63253df62f183e3dfa2770 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:14:45 -0500 Subject: Fix whitespace issues. --- board/mpc8641hpcn/init.S | 1 - 1 file changed, 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index c6ea55e..6b3e2d2 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -177,4 +177,3 @@ law_entry: stwu r6, 0x20(r5) blr - -- cgit v1.1 From bf651baa365e5447246aad6a633ccd667cf24a39 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 11 Oct 2006 10:10:43 -0500 Subject: Move "ar" flags to config.mk to allow for silent "make -s" --- board/mpc8641hpcn/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc8641hpcn') diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 46214ed..4b68c36 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) -- cgit v1.1