From 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a Mon Sep 17 00:00:00 2001 From: wdenk Date: Sun, 1 Aug 2004 23:02:45 +0000 Subject: Patch by Jon Loeliger, 16 Jul 2004: - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads --- board/mpc8560ads/flash.c | 2 - board/mpc8560ads/init.S | 320 +++++++++++++++++++++++++----------------- board/mpc8560ads/mpc8560ads.c | 186 ++++++++++++++++-------- 3 files changed, 322 insertions(+), 186 deletions(-) (limited to 'board/mpc8560ads') diff --git a/board/mpc8560ads/flash.c b/board/mpc8560ads/flash.c index c9dfb4d..4dbbf9d 100644 --- a/board/mpc8560ads/flash.c +++ b/board/mpc8560ads/flash.c @@ -86,14 +86,12 @@ unsigned long flash_init (void) flash_info[0].size = size; -#if !defined(CONFIG_RAM_AS_FLASH) #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, CFG_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); -#endif #ifdef CFG_ENV_IS_IN_FLASH /* ENV protection ON by default */ diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S index 99c4d79..242cb9f 100644 --- a/board/mpc8560ads/init.S +++ b/board/mpc8560ads/init.S @@ -1,26 +1,26 @@ /* * Copyright 2004 Freescale Semiconductor. -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ #include #include @@ -29,6 +29,24 @@ #include #include + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + #define entry_start \ mflr r1 ; \ bl 0f ; @@ -38,119 +56,174 @@ mtlr r1 ; \ blr ; -/* TLB1 entries configuration: */ .section .bootpg, "ax" .globl tlb1_entry tlb1_entry: entry_start - /* Number of entries in the following table */ - .long 0x0c - - .long TLB1_MAS0(1,1,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - #if defined(CFG_FLASH_PORT_WIDTH_16) - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) - #else - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif - - #if !defined(CONFIG_SPD_EEPROM) - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif - - .long TLB1_MAS0(1,6,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - #if defined(CONFIG_RAM_AS_FLASH) - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - #else - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - #endif - .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,7,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - #ifdef CONFIG_L2_INIT_RAM - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) - #else - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) - #endif - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,8,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,9,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif /* - * RapidIO MMU for 512M - * Two entries, 10 and 11 + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. */ - .long TLB1_MAS0(1,10,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) - .long TLB1_MAS0(1,11,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) -#else - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) #endif + entry_end /* @@ -184,13 +257,8 @@ tlb1_entry: /* * This is not so much the SDRAM map as it is the whole localbus map. */ -#if !defined(CONFIG_RAM_AS_FLASH) #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR2 0 -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index a0f6b97..ed7139d 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -26,6 +26,7 @@ #include +#include #include #include #include @@ -38,6 +39,7 @@ extern void ddr_enable_ecc(unsigned int dram_size); extern long int spd_sdram(void); +void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); @@ -209,16 +211,17 @@ typedef struct bcsr_ { volatile unsigned char bcsr5; } bcsr_t; + int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; - pci->peer &= 0xffffffdf; /* disable master abort */ + pci->peer &= 0xffffffdf; /* disable master abort */ #endif - return 0; + return 0; } void reset_phy (void) @@ -247,6 +250,7 @@ void reset_phy (void) #endif /* CONFIG_MII */ } + int checkboard (void) { puts("Board: ADS\n"); @@ -257,6 +261,12 @@ int checkboard (void) #else printf(" PCI1: disabled\n"); #endif + + /* + * Initialize local bus. + */ + local_bus_init(); + return 0; } @@ -272,15 +282,15 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); } #endif @@ -308,55 +318,79 @@ initdram(int board_type) /* - * Initialize SDRAM memory on the Local Bus. + * Initialize Local Bus */ -void sdram_init (void) +void +local_bus_init(void) { -#if !defined(CONFIG_RAM_AS_FLASH) - sys_info_t sysinfo; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - - puts (" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - /* - * LocalBus SDRAM is not emulating flash. - */ + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; /* - * Fix Local Bus clock glitch. Errata LBC11. + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is less than 66Mhz, use bypass mode, - * otherwise use DLL. - * lcrr is the local-bus clock ratio register. + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. */ - get_sys_info (&sysinfo); - if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000; + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* * On REV1 boards, need to change CLKDIV before enable DLL. * Default CLKDIV is 8, change it to 4 temporarily. */ - volatile ccsr_gur_t *gur = &immap->im_gur; - uint pvr = get_pvr (); + uint pvr = get_pvr(); uint temp_lbcdll = 0; if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ lbc->lcrr = 0x10000004; } - /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */ - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay (200); + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000; - asm ("sync;isync;msync"); + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); } +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts(" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers @@ -364,46 +398,44 @@ void sdram_init (void) lbc->or2 = CFG_OR2_PRELIM; lbc->br2 = CFG_BR2_PRELIM; lbc->lbcr = CFG_LBC_LBCR; - asm ("msync"); + asm("msync"); lbc->lsrt = CFG_LBC_LSRT; lbc->mrtpr = CFG_LBC_MRTPR; - asm ("sync"); + asm("sync"); /* * Configure the SDRAM controller. */ lbc->lsdmr = CFG_LBC_LSDMR_1; - asm ("sync"); + asm("sync"); *sdram_addr = 0xff; - ppcDcbf ((unsigned long) sdram_addr); - udelay (100); + ppcDcbf((unsigned long) sdram_addr); + udelay(100); lbc->lsdmr = CFG_LBC_LSDMR_2; - asm ("sync"); + asm("sync"); *sdram_addr = 0xff; - ppcDcbf ((unsigned long) sdram_addr); - udelay (100); + ppcDcbf((unsigned long) sdram_addr); + udelay(100); lbc->lsdmr = CFG_LBC_LSDMR_3; - asm ("sync"); + asm("sync"); *sdram_addr = 0xff; - ppcDcbf ((unsigned long) sdram_addr); - udelay (100); + ppcDcbf((unsigned long) sdram_addr); + udelay(100); lbc->lsdmr = CFG_LBC_LSDMR_4; - asm ("sync"); + asm("sync"); *sdram_addr = 0xff; - ppcDcbf ((unsigned long) sdram_addr); - udelay (100); + ppcDcbf((unsigned long) sdram_addr); + udelay(100); lbc->lsdmr = CFG_LBC_LSDMR_5; - asm ("sync"); + asm("sync"); *sdram_addr = 0xff; - ppcDcbf ((unsigned long) sdram_addr); - udelay (100); - -#endif + ppcDcbf((unsigned long) sdram_addr); + udelay(100); } @@ -476,3 +508,41 @@ long int fixed_sdram (void) return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} -- cgit v1.1