From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 30 Apr 2007 13:59:50 -0500 Subject: Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi Acked-by: Michael Benedict Signed-off-by: Kim Phillips --- board/mpc8349itx/mpc8349itx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'board/mpc8349itx/mpc8349itx.c') diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 2b3ded1..178b1d3 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -80,8 +80,7 @@ int fixed_sdram(void) im->ddr.sdram_interval = (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = - DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; udelay(200); -- cgit v1.1