From f2e4d6a58cafb219b1850c3db1238887109cd94d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Dec 2014 14:09:22 +0100 Subject: arm: mx6: novena: Pull video handling into separate file Pull all of the video handling into a separate file, since a lot more code will be added and such code would polute the board file. Signed-off-by: Marek Vasut Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Sean Cross Cc: Simon Glass Cc: Stefano Babic Cc: Tim Harvey --- board/kosagi/novena/novena.c | 79 +------------------------------------------- 1 file changed, 1 insertion(+), 78 deletions(-) (limited to 'board/kosagi/novena/novena.c') diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 5493e07..e7a6adb 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -152,87 +152,10 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Video over HDMI - */ -#if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = { - { - /* HDMI Output */ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } - } -}; - -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB0,IPU,IPU DI0 clocks */ - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); - - /* set LDB0, LDB1 clk select to 011/011 */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, - (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); - - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, - &iomux->gpr[2]); - - clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, - IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); -} -#endif - int board_early_init_f(void) { #if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + setup_display_clock(); #endif return 0; -- cgit v1.1