From d1c3b27525b664e8c4db6bb173eed51bfc8220de Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Sep 2009 16:25:29 +0200 Subject: ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese --- board/jse/sdram.c | 80 +++++++++++++++++++++++++++---------------------------- 1 file changed, 40 insertions(+), 40 deletions(-) (limited to 'board/jse/sdram.c') diff --git a/board/jse/sdram.c b/board/jse/sdram.c index a1f526d..bb6f85e 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -35,60 +35,60 @@ phys_size_t initdram (int board_type) /* Configure the SDRAMS */ /* disable memory controller */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besra); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besra); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besrb); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besrb); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (memcfga, mem_eccerr); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_eccerr); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x010a4016); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, 0x010a4016); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00084001); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, 0x00084001); /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, 0x04084001); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, 0x04084001); /* Memory Bank 2 Config == BE=0 */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Memory Bank 3 Config == BE=0 */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* refresh timer = 0x400 */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x04000000); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, 0x04000000); /* Power management idle timer set to the default. */ - mtdcr (memcfga, mem_pmit); - mtdcr (memcfgd, 0x07c00000); + mtdcr (SDRAM0_CFGADDR, mem_pmit); + mtdcr (SDRAM0_CFGDATA, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x80e00000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x80e00000); return SDRAM_LEN; } @@ -108,28 +108,28 @@ int testdram (void) #ifdef DEBUG printf ("SDRAM Controller Registers --\n"); - mtdcr (memcfga, mem_mcopt1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_CFG : 0x%08x\n", val); - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_STATUS: 0x%08x\n", val); - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B0CR : 0x%08x\n", val); - mtdcr (memcfga, mem_mb1cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B1CR : 0x%08x\n", val); - mtdcr (memcfga, mem_sdtr1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_TR : 0x%08x\n", val); - mtdcr (memcfga, mem_rtr); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_RTR : 0x%08x\n", val); #endif @@ -137,8 +137,8 @@ int testdram (void) bit. Really, there should already have been plenty of time, given it was started long ago. But, best to check. */ for (idx = 0; idx < 1000000; idx += 1) { - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); if (val & 0x80000000) break; } -- cgit v1.1