From cf6eb6da433179674571f9370566b1ec8989a41a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 14 Apr 2010 13:57:18 +0200 Subject: ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese --- board/gdsys/gdppc440etx/init.S | 16 ++++++++-------- board/gdsys/intip/init.S | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-) (limited to 'board/gdsys') diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S index 0bbd45a..ba750cb 100644 --- a/board/gdsys/gdppc440etx/init.S +++ b/board/gdsys/gdppc440etx/init.S @@ -51,25 +51,25 @@ tlbtab: * the speed up boot process. It is patched after relocation to enable SA_I */ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, - 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + 0, AC_RWX | SA_G/*|SA_I*/) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_R|AC_W|AC_X|SA_G ) + 0, AC_RWX | SA_G ) tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, - 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + 0, AC_RWX | SA_IG ) tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) /* PCI */ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbtab_end diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S index a8e8b6c..5a819c2 100644 --- a/board/gdsys/intip/init.S +++ b/board/gdsys/intip/init.S @@ -51,7 +51,7 @@ tlbtab: * enable SA_I */ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ + 4, AC_RWX | SA_G) /* TLB 0 */ /* * TLB entries for SDRAM are not needed on this platform. @@ -62,36 +62,36 @@ tlbtab: #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_R|AC_W|AC_X|SA_G) + 0, AC_RWX | SA_G) #endif tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, - AC_R|AC_W|SA_G|SA_I) + AC_RW | SA_IG) tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, - AC_R|AC_W|SA_G|SA_I) + AC_RW | SA_IG) /* TLB-entry for NVRAM */ tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4, - AC_R|AC_W|SA_G|SA_I) + AC_RW | SA_IG) /* TLB-entry for UART */ tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4, - AC_R|AC_W|SA_G|SA_I) + AC_RW | SA_IG) /* TLB-entry for IO */ tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4, - AC_R|AC_W|SA_G|SA_I) + AC_RW | SA_IG) /* TLB-entry for OCM */ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, - AC_R|AC_W|AC_X|SA_I) + AC_RWX | SA_I) /* TLB-entry for Local Configuration registers => peripherals */ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, - 4, AC_R|AC_W|AC_X|SA_G|SA_I) + 4, AC_RWX | SA_IG) /* AHB: Internal USB Peripherals (USB, SATA) */ tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, - AC_R|AC_W|AC_X|SA_G|SA_I) + AC_RWX | SA_IG) tlbtab_end -- cgit v1.1