From ed9e4e427295623197d8dd76a1ca9ac15e085572 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 27 Oct 2014 11:31:32 -0700 Subject: mpc85xx/t208xqds: Adjust DDR timing parameters Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of 1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in case such DIMM comes available. Also update single-rank 1866 timing. Enable interactive debugging as well. Signed-off-by: York Sun CC: Shengzhou Liu --- board/freescale/t208xqds/ddr.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index ed52fef6..9c26fdf 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -28,17 +28,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; -- cgit v1.1