From 3d7506fa380c2c3757947871a2ba4bd6401d8387 Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Wed, 18 Apr 2012 19:39:53 +0000 Subject: powerpc/85xx: Add USB device-tree fixup for various platforms Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh --- board/freescale/mpc8536ds/mpc8536ds.c | 7 ++++++- board/freescale/p1022ds/p1022ds.c | 6 +++++- board/freescale/p1023rds/p1023rds.c | 5 ++++- board/freescale/p2020come/p2020come.c | 4 +++- board/freescale/p2020ds/p2020ds.c | 6 +++++- board/freescale/p2041rdb/p2041rdb.c | 6 +++++- board/freescale/p3060qds/p3060qds.c | 6 +++++- 7 files changed, 33 insertions(+), 7 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 6d0bfde..7898708 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -290,5 +290,10 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + +#ifdef CONFIG_HAS_FSL_MPH_USB + fdt_fixup_dr_usb(blob, bd); +#endif + } #endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index aca30f3..56dfcce 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan * Timur Tabi * @@ -337,6 +337,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 082976a..eb11f3f 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang * Chunhe Lan @@ -202,6 +202,9 @@ void ft_board_setup(void *blob, bd_t *bd) do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); #endif +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif fdt_fixup_fman_ethernet(blob); } diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index 8cf7bee..ba4ef87 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -282,6 +282,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e8d31a4..3188f59 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -257,6 +257,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 976c8d2..d2732f5 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -211,6 +211,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c index c7cca2a..43e7f28 100644 --- a/board/freescale/p3060qds/p3060qds.c +++ b/board/freescale/p3060qds/p3060qds.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -323,6 +323,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif -- cgit v1.1 From 7530d341c70511902fdb4b97f596ef3b9a9c52be Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 24 Apr 2012 20:17:15 +0000 Subject: powerpc/mpc85xx:Add BSC9131 RDB Support BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements BSC9131RDB Overview ----------------- -1Gbyte DDR3 (on board DDR) -128Mbyte 2K page size NAND Flash -256 Kbit M24256 I2C EEPROM -128 Mbit SPI Flash memory -USB-ULPI -eTSEC1: Connected to RGMII PHY -eTSEC2: Connected to RGMII PHY -DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Ramneek Mehresh Signed-off-by: Priyanka Jain Signed-off-by: Akhil Goyal Signed-off-by: Rajan Srivastava Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha --- board/freescale/bsc9131rdb/Makefile | 53 +++++++++ board/freescale/bsc9131rdb/README | 137 +++++++++++++++++++++++ board/freescale/bsc9131rdb/bsc9131rdb.c | 83 ++++++++++++++ board/freescale/bsc9131rdb/ddr.c | 187 ++++++++++++++++++++++++++++++++ board/freescale/bsc9131rdb/law.c | 31 ++++++ board/freescale/bsc9131rdb/tlb.c | 67 ++++++++++++ 6 files changed, 558 insertions(+) create mode 100644 board/freescale/bsc9131rdb/Makefile create mode 100644 board/freescale/bsc9131rdb/README create mode 100644 board/freescale/bsc9131rdb/bsc9131rdb.c create mode 100644 board/freescale/bsc9131rdb/ddr.c create mode 100644 board/freescale/bsc9131rdb/law.c create mode 100644 board/freescale/bsc9131rdb/tlb.c (limited to 'board/freescale') diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile new file mode 100644 index 0000000..6f4cb26 --- /dev/null +++ b/board/freescale/bsc9131rdb/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +#COBJS-y += bsc9131rdb_mux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README new file mode 100644 index 0000000..065faa3 --- /dev/null +++ b/board/freescale/bsc9131rdb/README @@ -0,0 +1,137 @@ +Overview +-------- +- BSC9131 is integrated device that targets Femto base station market. + It combines Power Architecture e500v2 and DSP StarCore SC3850 core + technologies with MAPLE-B2F baseband acceleration processing elements. +- It's MAPLE disabled personality is called 9231. + +The BSC9131 SoC includes the following function and features: +. Power Architecture subsystem including a e500 processor with 256-Kbyte shared + L2 cache +. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache +. The Multi Accelerator Platform Engine for Femto BaseStation Baseband + Processing (MAPLE-B2F) +. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, + Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, + and CRC algorithms +. Consists of accelerators for Convolution, Filtering, Turbo Encoding, + Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion + operations +. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with + ECC, up to 400-MHz clock/800 MHz data rate +. Dedicated security engine featuring trusted boot +. DMA controller +. OCNDMA with four bidirectional channels +. Interfaces +. Two triple-speed Gigabit Ethernet controllers featuring network acceleration + including IEEE 1588. v2 hardware support and virtualization (eTSEC) +. eTSEC 1 supports RGMII/RMII +. eTSEC 2 supports RGMII +. High-speed USB 2.0 host and device controller with ULPI interface +. Enhanced secure digital (SD/MMC) host controller (eSDHC) +. Antenna interface controller (AIC), supporting three industry standard + JESD207/three custom ADI RF interfaces (two dual port and one single port) + and three MAXIM's MaxPHY serial interfaces +. ADI lanes support both full duplex FDD support and half duplex TDD support +. Universal Subscriber Identity Module (USIM) interface that facilitates + communication to SIM cards or Eurochip pre-paid phone cards +. TDM with one TDM port +. Two DUART, four eSPI, and two I2C controllers +. Integrated Flash memory controller (IFC) +. TDM with 256 channels +. GPIO +. Sixteen 32-bit timers + +The e500 core subsystem within the Power Architecture consists of the following: +. 32-Kbyte L1 instruction cache +. 32-Kbyte L1 data cache +. 256-Kbyte L2 cache/L2 memory/L2 stash +. programmable interrupt controller (PIC) +. Debug support +. Timers + +The SC3850 core subsystem consists of the following: +. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) +. 32 Kbyte 8-way level 1 data cache (L1 DCache) +. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) +. Memory management unit (MMU) +. Enhanced programmable interrupt controller (EPIC) +. Debug and profiling unit (DPU) +. Two 32-bit timers + +BSC9131RDB board Overview +------------------------- + 1Gbyte DDR3 (on board DDR) + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + USB-ULPI + eTSEC1: Connected to RGMII PHY + eTSEC2: Connected to RGMII PHY + DUART interface: supports one UARTs up to 115200 bps for console display + USIM connector + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. 1000/500/800 +2. 800/400/667 + +Boot Methods Supported +----------------------- +1. NAND Flash +2. SPI Flash + +Default Boot Method +-------------------- +NAND boot + +Building U-boot +-------------- +To build the u-boot for BSC9131RDB: +1. NAND Flash + make BSC9131RDB_NAND +2. SPI Flash + make BSC9131RDB_SPIFLASH + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable + 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K + 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9131rdb.dtb + bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c new file mode 100644 index 0000000..2e0e55f --- /dev/null +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -0,0 +1,83 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | + MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); + setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | + MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, + MPC85xx_PMUXCR_IFC_AD_GPIO | + MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); + + return 0; +} + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB\n", cpu->name); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c new file mode 100644 index 0000000..c753edf --- /dev/null +++ b/board/freescale/bsc9131rdb/ddr.c @@ -0,0 +1,187 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) { + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + } + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J256M8HX-15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c new file mode 100644 index 0000000..201c147 --- /dev/null +++ b/board/freescale/bsc9131rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c new file mode 100644 index 0000000..5b68f4a --- /dev/null +++ b/board/freescale/bsc9131rdb/tlb.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1) + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.1 From 487e8abbaa1ecf8f25dc1af3a572768cca3b094a Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 25 Apr 2012 23:43:24 +0000 Subject: powerpc/p1010rdb: update mux config of p1010rdb board On p1010rdb some signals are muxed for tdm/can/uart/flash. If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly, defaultly we keep spi chip selection to spi-flash instead of to tdm/slic and disable uart1 when not using flexcan, as well disable sdhc. Signed-off-by: Shengzhou Liu --- board/freescale/p1010rdb/p1010rdb.c | 56 +++++++++++++++++++++++++++++-------- 1 file changed, 44 insertions(+), 12 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 79a6ead..02ba740 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -252,6 +252,31 @@ void fdt_del_tdm(void *blob) } } +void fdt_del_sdhc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,esdhc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_disable_uart1(void *blob) +{ + int nodeoff; + + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", + CONFIG_SYS_NS16550_COM2); + + if (nodeoff > 0) { + fdt_status_disabled(blob, nodeoff); + } else { + printf("WARNING unable to set status for fsl,ns16550 " + "uart1: %s\n", fdt_strerror(nodeoff)); + } +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -281,19 +306,26 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_node_and_alias(blob, "ethernet2"); } #ifndef CONFIG_SDCARD + /* disable sdhc due to sdhc bug */ + fdt_del_sdhc(blob); if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - printf("fdt CAN"); fdt_del_tdm(blob); fdt_del_spi_slic(blob); - } -#ifndef CONFIG_SPIFLASH - else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - printf("fdt TDM"); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { fdt_del_flexcan(blob); fdt_del_spi_flash(blob); + fdt_disable_uart1(blob); + } else { + /* + * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" + * explicitly, defaultly spi_cs_sel to spi-flash instead of + * to tdm/slic. + */ + fdt_del_tdm(blob); + fdt_del_flexcan(blob); + fdt_disable_uart1(blob); } #endif -#endif } #endif @@ -309,10 +341,7 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - } -#ifndef CONFIG_SPIFLASH - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - printf("TDM"); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | @@ -321,8 +350,11 @@ int misc_init_r(void) setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - } -#endif + } else { + /* defaultly spi_cs_sel to flash */ + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + } + return 0; } #endif -- cgit v1.1 From d3de823e54899f00f8689b1acbe6701db8bad1f2 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 3 May 2012 16:51:10 +0000 Subject: powerpc/p1010rdb: add readme document for p1010rdb Signed-off-by: Shengzhou Liu --- board/freescale/p1010rdb/README | 212 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 board/freescale/p1010rdb/README (limited to 'board/freescale') diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README new file mode 100644 index 0000000..fcd8541 --- /dev/null +++ b/board/freescale/p1010rdb/README @@ -0,0 +1,212 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32 Mbyte NOR flash single-chip memory + - 32 Mbyte NAND flash memory + - 256 Kbit M24256 I2C EEPROM + - 16 Mbyte SPI memory + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - PCIe: + - Lane0: x1 mini-PCIe slot + - Lane1: x1 PCIe standard slot + - SATA: + - 1 internal SATA connector to 2.5” 160G SATA2 HDD + - 1 eSATA connector to rear panel + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - USB 2.0 port: + - x1 USB2.0 port via an external ULPI PHY to micro-AB connector + - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector + - FlexCAN ports: + - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + - RJ45 connectors are used for these 2 UART ports. + - TDM + - 2 FXS ports connected via an external SLIC to the TDM interface. + SLIC is controllled via SPI. + - 1 FXO port connected via a relay to FXS for switchover to POTS +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + - support critical POR setting changed via switch on board +PCB + - 6-layer routing (4-layer signals, 2-layer power and ground) + + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn u-boot to NOR flash +================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff80000 +$filesize + => erase eff80000 +$filesize + => cp.b $loadaddr eff80000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + +Alternate NOR bank +================== +1. Burn u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off eef80000 +$filesize + => erase eef80000 +$filesize + => cp.b $loadaddr eef80000 $filesize + +2. Switch to alternate NOR bank + => mw.b ffb00009 1 + => reset + or set SW1[8]= ON + +SW1[8]= OFF: Upper bank used for booting start +SW1[8]= ON: Lower bank used for booting start +CPLD NOR bank selection register address 0xFFB00009 Bit[0]: +0 - boot from upper 4 sectors +1 - boot from lower 4 sectors + + +Build and burn u-boot to NAND flash +=================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + + +Build and burn u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + + +CPLD POR setting registers +========================== +1. Set POR switch selection register (addr 0xFFB00011) to 0. +2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with + proper values. + If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 + switch command by I2C. +3. Send reset command. + After reset, the new POR setting will be implemented. + +Two examples are given in below: +Switch from NOR to NAND boot with default frequency: + => i2c dev 0 + => i2c mw 18 1 f9 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00017 1 + => reset +Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): + => i2c dev 0 + => i2c mw 18 1 f1 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00014 2 + => mw.b ffb00015 5 + => mw.b ffb00016 3 + => mw.b ffb00017 f + => reset + + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +Please contact your local field applications engineer or sales representative +to obtain related documents, such as P1010-RDB User Guide for details. + -- cgit v1.1 From 1fc0d59486571bad2a2c4e4a3e5c8b764c46b583 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 4 May 2012 12:21:28 +0000 Subject: powerpc/85xx: fdt_set_phy_handle() should return an error code fdt_set_phy_handle() makes several FDT calls that could fail, so it should not be hiding these errors. Signed-off-by: Timur Tabi --- board/freescale/common/fman.c | 36 +++++++++++++++++++----------------- board/freescale/common/fman.h | 2 +- 2 files changed, 20 insertions(+), 18 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 8a55fde..6ddf816 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -37,31 +37,33 @@ * ... update that Ethernet node's phy-handle property to point to the * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each * PHY in a virtual MDIO node must have an alias. + * + * Returns 0 on success, or a negative FDT error code on error. */ -void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, const char *alias) { - int offset, ph; + int offset; + unsigned int ph; const char *path; /* Get a path to the node that 'alias' points to */ path = fdt_get_alias(fdt, alias); - if (path) { - /* Get the offset of that node */ - int off = fdt_path_offset(fdt, path); - if (off > 0) - ph = fdt_create_phandle(fdt, off); - else - return; - } else { - return ; - } + if (!path) + return -FDT_ERR_BADPATH; + + /* Get the offset of that node */ + offset = fdt_path_offset(fdt, path); + if (offset < 0) + return offset; - /* failed to create a phandle */ - if (ph <= 0) - return ; + ph = fdt_create_phandle(fdt, offset); + if (!ph) + return -FDT_ERR_BADPHANDLE; offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); - if (offset > 0) - fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); + if (offset < 0) + return offset; + + return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); } diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h index 19ef7c4..d39ef08 100644 --- a/board/freescale/common/fman.h +++ b/board/freescale/common/fman.h @@ -20,7 +20,7 @@ #ifndef __FMAN_BOARD_HELPER__ #define __FMAN_BOARD_HELPER__ -void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, const char *alias); #endif -- cgit v1.1 From 48f6a5c348453fc3ab33aaa91e5e4198a28678ff Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 6 Jul 2012 17:10:33 -0500 Subject: powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER(). This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with encryption. Remove all _E entries from SVR list and CPU list. Signed-off-by: York Sun --- board/freescale/p1010rdb/ddr.c | 6 +++--- board/freescale/p1010rdb/p1010rdb.c | 4 ++-- board/freescale/p1_p2_rdb/ddr.c | 6 ++---- 3 files changed, 7 insertions(+), 9 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 36c8545..10c5a42 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -101,7 +101,7 @@ unsigned long get_sdram_size(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); else ddr_size = CONFIG_SYS_DRAM_SIZE; @@ -146,7 +146,7 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; @@ -238,7 +238,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 02ba740..dfeb86f 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -190,7 +190,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) { + if (cpu->soc_ver != SVR_P1014) { SET_STD_TSEC_INFO(tsec_info[num], 3); num++; } @@ -301,7 +301,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { fdt_del_flexcan(blob); fdt_del_node_and_alias(blob, "ethernet2"); } diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 71c6088..916439c 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -204,8 +204,7 @@ phys_size_t fixed_sdram (void) cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } else { ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; @@ -232,8 +231,7 @@ phys_size_t fixed_sdram (void) strmhz(buf, ddr_freq)); /* P1020 and it's derivatives support max 32bit DDR width */ - if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; } -- cgit v1.1