From ab06b236f76cfa42f264ee161be190b3e479298f Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Fri, 12 Sep 2014 14:47:09 +0800 Subject: powerpc/t4rdb: Add support of CPLD This support of CPLD includes - Files and register definitions - Command to switch alternate bank - Command to switch default bank Signed-off-by: Chunhe Lan Reviewed-by: York Sun --- board/freescale/t4rdb/Makefile | 1 + board/freescale/t4rdb/cpld.c | 136 +++++++++++++++++++++++++++++++++++++++ board/freescale/t4rdb/cpld.h | 49 ++++++++++++++ board/freescale/t4rdb/law.c | 3 + board/freescale/t4rdb/t4240rdb.c | 12 ++++ board/freescale/t4rdb/tlb.c | 5 ++ 6 files changed, 206 insertions(+) create mode 100644 board/freescale/t4rdb/cpld.c create mode 100644 board/freescale/t4rdb/cpld.h (limited to 'board/freescale') diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index f7f7fc0..3886e3d 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,6 +5,7 @@ # obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c new file mode 100644 index 0000000..d5f3812 --- /dev/null +++ b/board/freescale/t4rdb/cpld.c @@ -0,0 +1,136 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK0; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h new file mode 100644 index 0000000..0180082 --- /dev/null +++ b/board/freescale/t4rdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 1f58768..39818fc 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -16,6 +16,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index afef7e9..2ff77b8 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -20,14 +20,26 @@ #include #include "t4rdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); puts("SERDES Reference Clocks:\n"); printf(" SERDES1=100MHz SERDES2=156.25MHz\n" diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 4b50bcd..474301e 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -106,6 +106,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.1 From 0921de67440ac5dfc3dbf687217cdecc6335f15e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 17 Sep 2014 15:57:54 +0530 Subject: t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg -A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase -A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/t104xrdb/t104x_pbi.cfg | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index 7b9e9b0..b83b9b7 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 -- cgit v1.1 From 42a9e2fe1be0f8879ad0928e05116e5a4c7cea1a Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Mon, 6 Oct 2014 18:24:56 +0530 Subject: powerpc/BSC9132QDS: Enable creation of dynamic partition for NAND and NOR * fdt_fixup_mtdparts is called from ft_board_setup * run "mtdparts default" to create NAND, NOR partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- board/freescale/bsc9132qds/bsc9132qds.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 10580bc..c88838b 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -21,6 +21,9 @@ #include #include #include +#include +#include +#include #ifdef CONFIG_PCI #include @@ -354,6 +357,12 @@ void fdt_del_node_compat(void *blob, const char *compatible) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "cfi-flash", MTD_DEV_TYPE_NOR, }, + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -369,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 porbmsr = in_be32(&gur->porbmsr); -- cgit v1.1 From 7ac1a24a85b9e961f8f26a9c2a23a438a849f183 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Tue, 7 Oct 2014 18:02:23 +0530 Subject: powerpc/BSC9131RDB: Enable creation of dynamic partitions for NAND * fdt_fixup_mtdparts is called from ft_board_setup * Run "mtdparts default" to create NAND partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- board/freescale/bsc9131rdb/bsc9131rdb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 7fe4ae7..9146f49 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -15,6 +15,9 @@ #include #include #include +#include +#include +#include #include @@ -50,6 +53,11 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -61,6 +69,9 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif fdt_fixup_dr_usb(blob, bd); } -- cgit v1.1