From e55782ecccadc196a4f9d8e5e8b456e200ea9727 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 27 Jun 2014 14:39:31 +0800 Subject: powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- board/freescale/t4qds/t4240qds.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'board/freescale/t4qds/t4240qds.c') diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index c5161c8..6205fea 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -644,9 +644,10 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; u32 actual[MAX_SERDES]; + u32 pllcr0, expected; unsigned int i; sw = QIXIS_READ(brdcfg[2]); @@ -669,8 +670,9 @@ int misc_init_r(void) } for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), -- cgit v1.1