From ef531c73570794b7676b62de4224bd294919b83b Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 18 Apr 2014 16:43:41 +0800 Subject: board/t2080rdb: some update for t2080rdb - update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t208xrdb/cpld.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/freescale/t208xrdb/cpld.h') diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 4cee4e5..3f15338 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_MASK 0x3F #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 -- cgit v1.1