From 6666017f44e39ec0385e3c7736b8c9af46cf4f08 Mon Sep 17 00:00:00 2001
From: vijay rai <vijay.rai@freescale.com>
Date: Fri, 20 Jun 2014 10:45:29 +0530
Subject: powerpc/t1040qds: Initialize EPHY2 clock to RGMII only

Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 board/freescale/t1040qds/eth.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'board/freescale/t1040qds/eth.c')

diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 3077b4a..1929bba 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -355,7 +355,9 @@ static void set_brdcfg9_for_gtx_clk(void)
 {
 	u8 brdcfg9;
 	brdcfg9 = QIXIS_READ(brdcfg[9]);
-	brdcfg9 |= (1 << 5);
+/* Initializing EPHY2 clock to RGMII mode */
+	brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
+	brdcfg9 |= (BRDCFG9_EPHY2_VAL);
 	QIXIS_WRITE(brdcfg[9], brdcfg9);
 }
 
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