From 534992827756c3a1ab49823ca487702a954fe433 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Tue, 31 May 2016 15:39:06 +0800 Subject: board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t102xrdb/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/freescale/t102xrdb') diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index adf9fd5..b13692b 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -234,12 +234,12 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); #endif dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); -- cgit v1.1