From 44d50f0b54ef14534440bc5d789ec65240dfc0f8 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2011 17:55:11 +0800 Subject: powerpc/p2041rdb: set sysclk according to status of physical switch SW1 P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- board/freescale/p2041rdb/cpld.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board/freescale/p2041rdb/cpld.h') diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h index dcdb410..bece5dd 100644 --- a/board/freescale/p2041rdb/cpld.h +++ b/board/freescale/p2041rdb/cpld.h @@ -30,6 +30,7 @@ typedef struct cpld_data { u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ u8 sw[1]; /* 0xd - SW2 Status */ u8 system_rst_default; /* 0xe - system reset to default register */ + u8 sysclk_sw1; /* 0xf - sysclk configuration register */ } __attribute__ ((packed)) cpld_data_t; #define SERDES_MUX_LANE_6_MASK 0x2 @@ -41,6 +42,8 @@ typedef struct cpld_data { #define SERDES_MUX_LANE_D_MASK 0x8 #define SERDES_MUX_LANE_D_SHIFT 3 #define CPLD_SWITCH_BANK_ENABLE 0x40 +#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */ +#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */ /* Pointer to the CPLD register set */ #define cpld ((cpld_data_t *)CPLD_BASE) -- cgit v1.1