From aad4659a2fde4b69e8124d6fe8b57bf28d3c747d Mon Sep 17 00:00:00 2001 From: Abbas Raza Date: Mon, 25 Mar 2013 09:13:34 +0000 Subject: mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza cc: stefano Babic cc: Andy Fleming Acked-by: Dirk Behme Acked-by: Andrew Gabbasov --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board/freescale/mx6qsabrelite/mx6qsabrelite.c') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 5b69a6d..0e25613 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].max_bus_width = 4; + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: -- cgit v1.1