From 46f3e3851dac0c4acecf4192d8e13c8521ce98b4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 9 Jul 2010 00:02:34 -0500 Subject: powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641 The MPC8641 boards actually only have PCIE not PCI. Rename so we are uniform with regards to names so we can replace this code with templated code. Signed-off-by: Kumar Gala --- board/freescale/mpc8641hpcn/law.c | 18 +++++----- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 58 +++++++++++++++---------------- 2 files changed, 38 insertions(+), 38 deletions(-) (limited to 'board/freescale/mpc8641hpcn') diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index bd357b8..8c8ce95 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -32,14 +32,14 @@ * * 0x0000_0000 0x7fff_ffff DDR 2G * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) * 0x8000_0000 0x9fff_ffff RapidIO 512M * endif * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) - * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K - * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K + * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K + * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K * 0xffe0_0000 0xffef_ffff CCSRBAR 1M * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M @@ -54,10 +54,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif #ifdef CONFIG_PCI - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), #elif defined(CONFIG_RIO) SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 9e88102..a88be5a 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2007 Freescale Semiconductor. + * Copyright 2006, 2007, 2010 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -129,21 +129,21 @@ fixed_sdram(void) #if defined(CONFIG_PCI) -static struct pci_controller pci1_hose; +static struct pci_controller pcie1_hose; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif /* CONFIG_PCIE2 */ int first_free_busno = 0; void pci_init_board(void) { -#ifdef CONFIG_PCI1 +#ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pci1_hose; + struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -169,16 +169,16 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, + CONFIG_SYS_PCIE1_MEM_BUS, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, + CONFIG_SYS_PCIE1_IO_BUS, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -195,8 +195,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT - + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT + + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); @@ -204,26 +204,26 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ +#endif /* CONFIG_PCIE1 */ -#ifdef CONFIG_PCI2 +#ifdef CONFIG_PCIE2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pci2_hose; + struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BUS, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, + CONFIG_SYS_PCIE2_MEM_BUS, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BUS, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, + CONFIG_SYS_PCIE2_IO_BUS, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -238,7 +238,7 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ +#endif /* CONFIG_PCIE2 */ } @@ -253,11 +253,11 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci0", &pcie1_hose); #endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); #endif /* -- cgit v1.1