From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/freescale/mpc8568mds/bcsr.c | 14 +++--- board/freescale/mpc8568mds/law.c | 12 ++--- board/freescale/mpc8568mds/mpc8568mds.c | 82 ++++++++++++++++----------------- board/freescale/mpc8568mds/tlb.c | 20 ++++---- 4 files changed, 64 insertions(+), 64 deletions(-) (limited to 'board/freescale/mpc8568mds') diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c index 791a50f..30676e1 100644 --- a/board/freescale/mpc8568mds/bcsr.c +++ b/board/freescale/mpc8568mds/bcsr.c @@ -27,9 +27,9 @@ void enable_8568mds_duart() { - volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060); - volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070); - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); + volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ *devices = 0; /* Enable all peripheral devices */ @@ -38,21 +38,21 @@ void enable_8568mds_duart() void enable_8568mds_flash_write() { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] |= 0x01; } void disable_8568mds_flash_write() { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] &= ~(0x01); } void enable_8568mds_qe_mdio() { - u8 *bcsr = (u8 *)(CFG_BCSR); + u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[7] |= 0x01; } @@ -60,7 +60,7 @@ void enable_8568mds_qe_mdio() #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) void reset_8568mds_uccs(void) { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); /* Turn off UCC1 & UCC2 */ out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index 3bc24c5..da7b6dc 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -50,13 +50,13 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index f9e35cc..eab1900 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -123,10 +123,10 @@ int board_early_init_f (void) enable_8568mds_qe_mdio(); #endif -#ifdef CFG_I2C2_OFFSET +#ifdef CONFIG_SYS_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ volatile struct par_io *port_c; - port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); port_c->cpdir2 |= 0x0f000000; port_c->cppar2 &= ~0x0f000000; port_c->cppar2 |= 0x0a000000; @@ -158,7 +158,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -192,8 +192,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -223,44 +223,44 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8568 uses "new" 15-16 style addressing. */ - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -270,7 +270,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -280,7 +280,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -289,7 +289,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -371,7 +371,7 @@ pib_init(void) void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -379,7 +379,7 @@ pci_init_board(void) { pib_init(); - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci1_hose; @@ -403,23 +403,23 @@ pci_init_board(void) /* inbound */ pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; @@ -440,7 +440,7 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); @@ -460,23 +460,23 @@ pci_init_board(void) /* inbound */ pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 7565176..1077552 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH (upper half) * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -55,7 +55,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLBe 1: 16M Non-cacheable, guarded * 0xfe000000 16M FLASH (lower half) */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0x80000000 512M PCI1 MEM * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), @@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_64M, 1), @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLBe 4: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), @@ -92,7 +92,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8008000 32K PIB (CS4) * 0xf8010000 32K PIB (CS5) */ - SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256K, 1), }; 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