From c8c41d4a80b1a8ad5984a287d81ea780496259f8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 10:04:42 -0600 Subject: 85xx: Use proper defines for PCI addresses We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala --- board/freescale/mpc8555cds/init.S | 16 ++++++++-------- board/freescale/mpc8555cds/law.c | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'board/freescale/mpc8555cds') diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S index 563ea2d..6e93fb0 100644 --- a/board/freescale/mpc8555cds/init.S +++ b/board/freescale/mpc8555cds/init.S @@ -130,8 +130,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -139,8 +139,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded @@ -148,8 +148,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 3, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded @@ -157,8 +157,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 4, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 5: 64M Non-cacheable, guarded diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c index a8aa4db..0ac223c 100644 --- a/board/freescale/mpc8555cds/law.c +++ b/board/freescale/mpc8555cds/law.c @@ -47,8 +47,8 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -- cgit v1.1