From 5af0fdd81c3370c3a51421208fda568bdcbbec23 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:39 -0600 Subject: 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8544ds/tlb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board/freescale/mpc8544ds') diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index c7442b2..d99441b 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -- cgit v1.1