From e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 4 May 2016 10:20:22 +0800 Subject: board/freescale: Update ddr clk_adjust This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/ls1043ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board/freescale/ls1043ardb/ddr.h') diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index 8ca166b..a77ddf3 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, #endif {} }; -- cgit v1.1