From 9d044fcb8c4558d7ec28089375d2de565bfd2619 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:34 +0530 Subject: armv8: ls1012a: Add support of ls1012aqds board QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Abhimanyu Saini Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- board/freescale/ls1012aqds/Kconfig | 15 ++ board/freescale/ls1012aqds/MAINTAINERS | 6 + board/freescale/ls1012aqds/Makefile | 7 + board/freescale/ls1012aqds/README | 59 +++++++ board/freescale/ls1012aqds/ls1012aqds.c | 234 ++++++++++++++++++++++++++ board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++ 6 files changed, 356 insertions(+) create mode 100644 board/freescale/ls1012aqds/Kconfig create mode 100644 board/freescale/ls1012aqds/MAINTAINERS create mode 100644 board/freescale/ls1012aqds/Makefile create mode 100644 board/freescale/ls1012aqds/README create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h (limited to 'board/freescale/ls1012aqds') diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig new file mode 100644 index 0000000..1257ec8 --- /dev/null +++ b/board/freescale/ls1012aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AQDS + +config SYS_BOARD + default "ls1012aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012aqds" + +endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS new file mode 100644 index 0000000..27c4aff --- /dev/null +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AQDS BOARD +M: Prabhakar Kushwaha +S: Maintained +F: board/freescale/ls1012aqds/ +F: include/configs/ls1012aqds.h +F: configs/ls1012aqds_qspi_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile new file mode 100644 index 0000000..0b813f9 --- /dev/null +++ b/board/freescale/ls1012aqds/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012aqds.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README new file mode 100644 index 0000000..dee4b30 --- /dev/null +++ b/board/freescale/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c new file mode 100644 index 0000000..71eea82 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -0,0 +1,234 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "ls1012aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + + if (sw & QIXIS_LBMAP_ALTBANK) + printf("flash: 2\n"); + else + printf("flash: 1\n"); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 mux_sdhc_cd = 0x80; + + i2c_set_bus_num(0); + + i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h new file mode 100644 index 0000000..584f604 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif -- cgit v1.1