From c37fdbdbb0dd65cb4aa147c9cf9352901014be3b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:24 +0800 Subject: fsl: csu: add an API to set individual device access permission Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/common/ns_access.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) (limited to 'board/freescale/common') diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index d8d16c5..c3d7a5e 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -9,25 +9,31 @@ #include #include -static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; - uint32_t val; - int i; + uint32_t tmp; - for (i = 0; i < num; i++) { - reg = base + ns_dev[i].ind / 2; - val = in_be32(reg); - if (ns_dev[i].ind % 2 == 0) { - val &= 0x0000ffff; - val |= ns_dev[i].val << 16; - } else { - val &= 0xffff0000; - val |= ns_dev[i].val; - } - out_be32(reg, val); + reg = base + ns_dev->ind / 2; + tmp = in_be32(reg); + if (ns_dev->ind % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; } + + out_be32(reg, tmp); +} + +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + int i; + + for (i = 0; i < num; i++) + set_devices_ns_access(ns_dev + i, ns_dev[i].val); } void enable_layerscape_ns_access(void) -- cgit v1.1 From 664b6520582fcea7e150f57258c7a63627837318 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:26 +0800 Subject: fsl: csu: add an API to set R/W permission to PCIe Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/common/ns_access.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'board/freescale/common') diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e..81c9211 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include #include #include +#include void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} -- cgit v1.1 From 214ffae02d03cd548549c6390eb9c19b9e6b085f Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Fri, 19 Aug 2016 17:20:33 +0800 Subject: nxp: ls102xa: add LS1 PSCI system suspend The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- board/freescale/common/arm_sleep.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'board/freescale/common') diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 71ed15e..16fd445 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -66,6 +66,36 @@ static void dp_ddr_restore(void) *dst++ = *src++; } +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +void ls1_psci_resume_fixup(void) +{ + u32 tmp; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef QIXIS_BASE + void *qixis_base = (void *)QIXIS_BASE; + + /* Pull on PCIe RST# */ + out_8(qixis_base + QIXIS_RST_FORCE_3, 0); + + /* disable deep sleep signals in FPGA */ + tmp = in_8(qixis_base + QIXIS_PWR_CTL2); + tmp &= ~QIXIS_PWR_CTL2_PCTL; + out_8(qixis_base + QIXIS_PWR_CTL2, tmp); +#endif + + /* Disable wakeup interrupt during deep sleep */ + out_be32(&scfg->pmcintecr, 0); + /* Clear PMC interrupt status */ + out_be32(&scfg->pmcintsr, 0xffffffff); + + /* Disable Warm Device Reset */ + tmp = in_be32(&scfg->dpslpcr); + tmp &= ~SCFG_DPSLPCR_WDRR_EN; + out_be32(&scfg->dpslpcr, tmp); +} +#endif + static void dp_resume_prepare(void) { dp_ddr_restore(); @@ -74,6 +104,9 @@ static void dp_resume_prepare(void) #ifdef CONFIG_U_QE u_qe_resume(); #endif +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) + ls1_psci_resume_fixup(); +#endif } int fsl_dp_resume(void) @@ -88,7 +121,7 @@ int fsl_dp_resume(void) dp_resume_prepare(); /* Get the entry address and jump to kernel */ - start_addr = in_le32(&scfg->sparecr[1]); + start_addr = in_le32(&scfg->sparecr[3]); debug("Entry address is 0x%08x\n", start_addr); kernel_resume = (void (*)(void))start_addr; secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); -- cgit v1.1 From 126fe70d7746d7e60a6331391cab6713368b78dc Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 7 Sep 2016 17:56:14 +0800 Subject: armv8: ls1046aqds: Add LS1046AQDS board support LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- board/freescale/common/vid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board/freescale/common') diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 2f29795..1a50304 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -8,7 +8,7 @@ #include #include #include -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 #include #elif defined(CONFIG_FSL_LSCH3) #include @@ -247,7 +247,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) * SoC before converting into an IR VID value */ vdd += board_vdd_drop_compensation(); -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 vid = DIV_ROUND_UP(vdd - 265, 5); #else vid = DIV_ROUND_UP(vdd - 245, 5); @@ -287,7 +287,7 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -386,7 +386,7 @@ int adjust_vdd(ulong vdd_override) * | T | | | | | * ------------------------------------------------------ */ -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { -- cgit v1.1