From 765b0bdb899d614d0455f19548901b79f2baa66c Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 4 Apr 2013 09:31:54 +0530 Subject: board/bsc9131rdb: Add DSP side tlb and laws BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- board/freescale/bsc9131rdb/law.c | 4 ++++ board/freescale/bsc9131rdb/tlb.c | 6 ++++++ 2 files changed, 10 insertions(+) (limited to 'board/freescale/bsc9131rdb') diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c index 201c147..0432780 100644 --- a/board/freescale/bsc9131rdb/law.c +++ b/board/freescale/bsc9131rdb/law.c @@ -26,6 +26,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M, + LAW_TRGT_IF_OCN_DSP), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 243a38f..8a7c0ec 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -52,6 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), + /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, -- cgit v1.1