From c5dfe6ec58e0b504cba5b429200f6a5d217d5bd9 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:13:44 +0530 Subject: board/b4qds:Add support of 2 stage NAND boot-loader Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- board/freescale/b4860qds/tlb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board/freescale/b4860qds/tlb.c') diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 00798a1..7b55b86 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for SRIO2. */ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_SYS_SRIO1_MEM_PHYS /* *I*G* - SRIO1 */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, @@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.1