From 882ae41274921f9016131806bdeb27e19606f47a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 15:44:39 +0200 Subject: ppc4xx: Rework of 4xx serial driver (2) Change all linker scripts to reference the changed driver name 4xx_uart.o. Note: In most cased all these explicit referencing of these object files in the linker scripts is not neccessary. Only for manually embedded environment into the U-Boot image, which is not done is most cases. Signed-off-by: Stefan Roese --- board/esd/plu405/u-boot.lds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/esd/plu405') diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) -- cgit v1.1 From f6e0f1f61896ce7729ba1bcea2ffbd138d3947f5 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 28 Dec 2007 17:10:36 +0100 Subject: ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates - add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: Matthias Fuchs --- board/esd/plu405/plu405.c | 95 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 89 insertions(+), 6 deletions(-) (limited to 'board/esd/plu405') diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index f026a7a..57762b5 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -109,8 +109,8 @@ int misc_init_f (void) int misc_init_r (void) { - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -184,16 +184,28 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* + * Set NAND-FLASH GPIO signals to default + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + + /* + * Setup EEPROM write protection + */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + + /* * Enable interrupts in exar duart mcr[3] */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; + out_8(duart0_mcr, 0x08); + out_8(duart1_mcr, 0x08); return (0); } @@ -259,3 +271,74 @@ void reset_phy(void) lxt971_no_sleep(); #endif } + + +#if defined(CFG_EEPROM_WREN) +/* Input: I2C address of EEPROM device to enable. + * -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO0. */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ -- cgit v1.1