From d1c3b27525b664e8c4db6bb173eed51bfc8220de Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 9 Sep 2009 16:25:29 +0200
Subject: ppc4xx: Big cleanup of PPC4xx defines

This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/esd/pci405/flash.c  |  8 ++++----
 board/esd/pci405/pci405.c | 28 ++++++++++++++--------------
 2 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'board/esd/pci405')

diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
index 9058483..67a7bb5 100644
--- a/board/esd/pci405/flash.c
+++ b/board/esd/pci405/flash.c
@@ -65,9 +65,9 @@ unsigned long flash_init (void)
 	flash_get_offsets (-size_b0, &flash_info[0]);
 
 	/* Re-do sizing to get full correct info */
-	mtdcr(ebccfga, pb0cr);
-	pbcr = mfdcr(ebccfgd);
-	mtdcr(ebccfga, pb0cr);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
 	base_b0 = -size_b0;
 	switch (size_b0) {
 	case 1 << 20:
@@ -87,7 +87,7 @@ unsigned long flash_init (void)
 		break;
 	}
 	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-	mtdcr(ebccfgd, pbcr);
+	mtdcr(EBC0_CFGDATA, pbcr);
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 56184ca..04bc569 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -67,7 +67,7 @@ const unsigned char fpgadata[] =
 
 int board_revision(void)
 {
-	unsigned long cntrl0Reg;
+	unsigned long CPC0_CR0Reg;
 	unsigned long value;
 
 	/*
@@ -77,8 +77,8 @@ int board_revision(void)
 	/*
 	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
 	 */
-	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
 	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
 	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
 	udelay(1000);                   /* wait some time before reading input */
@@ -87,7 +87,7 @@ int board_revision(void)
 	/*
 	 * Restore GPIO settings
 	 */
-	mtdcr(cntrl0, cntrl0Reg);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
 	switch (value) {
 	case 0x00100200:
@@ -133,7 +133,7 @@ unsigned long fpga_init_state(void)
 
 int board_early_init_f (void)
 {
-	unsigned long cntrl0Reg;
+	unsigned long CPC0_CR0Reg;
 
 	/*
 	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
@@ -166,18 +166,18 @@ int board_early_init_f (void)
 	/*
 	 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
 	 */
-	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x00008000);
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
 
 	/*
 	 * Setup GPIO pins (CS6+CS7 as GPIO)
 	 */
-	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
 	 */
-	mtebc (epcr, 0xa8400000); /* ebc always driven */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 
 	return 0;
 }
@@ -282,11 +282,11 @@ int misc_init_r (void)
 #define PCI0_BRDGOPT1 0x4a
 	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 
-#define plb0_acr      0x87
+#define PLB0_ACR      0x87
 	/*
 	 * Enable fairness and high bus utilization
 	 */
-	mtdcr(plb0_acr, 0x98000000);
+	mtdcr(PLB0_ACR, 0x98000000);
 
 	free(dst);
 	return (0);
@@ -313,14 +313,14 @@ int checkboard (void)
 	printf(" (Rev 1.%ld", gd->board_type);
 
 	if (gd->board_type >= 2) {
-		unsigned long cntrl0Reg;
+		unsigned long CPC0_CR0Reg;
 		unsigned long value;
 
 		/*
 		 * Setup GPIO pins (Trace/GPIO1 to GPIO)
 		 */
-		cntrl0Reg = mfdcr(cntrl0);
-		mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
+		CPC0_CR0Reg = mfdcr(CPC0_CR0);
+		mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
 		out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
 		out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
 		udelay(1000);                   /* wait some time before reading input */
-- 
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