From 82ceba2ca2487c4967419cf7053e1301709219e5 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 16 Mar 2016 08:48:21 +0100
Subject: x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support

This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 board/congatec/conga-qeval20-qa3-e3845/Kconfig     | 28 +++++++++++++++++++
 board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS |  7 +++++
 board/congatec/conga-qeval20-qa3-e3845/Makefile    |  7 +++++
 .../conga-qeval20-qa3-e3845/conga-qeval20-qa3.c    | 31 ++++++++++++++++++++++
 board/congatec/conga-qeval20-qa3-e3845/start.S     |  9 +++++++
 5 files changed, 82 insertions(+)
 create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Kconfig
 create mode 100644 board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
 create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Makefile
 create mode 100644 board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
 create mode 100644 board/congatec/conga-qeval20-qa3-e3845/start.S

(limited to 'board/congatec/conga-qeval20-qa3-e3845')

diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
new file mode 100644
index 0000000..9f31238
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_CONGA_QEVAL20_QA3_E3845
+
+config SYS_BOARD
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !EFI_STUB
+	default 0x01110000 if EFI_STUB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR if !EFI_STUB
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
new file mode 100644
index 0000000..5a4d4dc
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -0,0 +1,7 @@
+congatec EVAL20-QA3-E3845
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/congatec/conga-qeval20-qa3-e3845
+F:	include/configs/conga-qeval20-qa3-e3845.h
+F:	configs/conga-qeval20-qa3-e3845_defconfig
+F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
new file mode 100644
index 0000000..23b8748
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= conga-qeval20-qa3.o start.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
new file mode 100644
index 0000000..6a946d5
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <winbond_w83627.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Winbond one can be used.
+	 */
+	setup_internal_uart(0);
+
+	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
+	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
+			      UART0_BASE, UART0_IRQ);
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
diff --git a/board/congatec/conga-qeval20-qa3-e3845/start.S b/board/congatec/conga-qeval20-qa3-e3845/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
-- 
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