From d9b94f28a442b0013caef99de084d7b72e2d4607 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 25 Jul 2005 14:05:07 -0500 Subject: * Patch by Jon Loeliger, 2005-05-05 Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O --- board/cds/mpc8555cds/mpc8555cds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/cds/mpc8555cds/mpc8555cds.c') diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index a40de21..18adf5b 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -30,7 +30,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -269,7 +269,7 @@ initdram(int board_type) #endif dram_size = spd_sdram(); -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ -- cgit v1.1