From 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Thu, 14 Dec 2006 14:14:55 +0800 Subject: u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang --- board/cds/mpc8548cds/init.S | 77 ++++++++++++++++++++++++----------------- board/cds/mpc8548cds/u-boot.lds | 1 + 2 files changed, 46 insertions(+), 32 deletions(-) (limited to 'board/cds/mpc8548cds') diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 978bda5..2c15deb 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -64,8 +64,9 @@ tlb1_entry: /* * Number of TLB0 and TLB1 entries in the following table */ - .long 13 + .long (2f-1f)/16 +1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* * TLB0 4K Non-cacheable, guarded @@ -134,7 +135,7 @@ tlb1_entry: /* * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * 0x80000000 256M PCI1 MEM */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) @@ -143,40 +144,37 @@ tlb1_entry: /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half + * 0x90000000 256M PCI2 MEM */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half + * TLB 3: 1GB Non-cacheable, guarded + * 0xa0000000 256M PEX MEM First half + * 0xb0000000 256M PEX MEM Second half + * 0xc0000000 256M Rapid IO MEM First half + * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half + * TLB 4: Reserved for future usage */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCI2 IO + * 0xe300_0000 16M PEX IO */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) @@ -200,19 +198,22 @@ tlb1_entry: .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) - +2: entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M + * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M + * 0xa000_0000 0xbfff_ffff PEX MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M + * 0xe300_0000 0xe3ff_ffff PEX IO 16M + * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M @@ -229,27 +230,39 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .section .bootpg, "ax" .globl law_entry law_entry: entry_start - .long 6 + .long (4f-3f)/8 +3: .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 + .long LAWBAR8,LAWAR8 +4: entry_end diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds index 2c8fe96..c1f3495 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/cds/mpc8548cds/u-boot.lds @@ -69,6 +69,7 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) + drivers/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) -- cgit v1.1 From 7337b237ffc4aaf1b9467024fe472a880d852598 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Fri, 15 Dec 2006 14:43:31 +0800 Subject: u-boot: Fix CPU2 errata on MPC8548CDS board This patch apply workaround of CPU2 errata on MPC8548CDS board. Signed-off-by:Ebony Zhu --- board/cds/mpc8548cds/mpc8548cds.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board/cds/mpc8548cds') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 7433ebf..0d3fceb 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -51,6 +51,7 @@ int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -89,6 +90,12 @@ int checkboard (void) */ local_bus_init (); + /* + * Fix CPU2 errata: A core hang possible while executing a + * msync instruction and a snoopable transaction from an I/O + * master tagged to make quick forward progress is present. + */ + ecm->eebpcr |= (1 << 16); /* * Hack TSEC 3 and 4 IO voltages. -- cgit v1.1 From 45cef612cc601d2d1c890fbbd7cdc9609a189a46 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:11:16 -0600 Subject: Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming --- board/cds/mpc8548cds/init.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/cds/mpc8548cds') diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 2c15deb..34ca711 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -161,7 +161,7 @@ tlb1_entry: * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) -- cgit v1.1 From ffa621a0d12a1ccd81c936c567f8917a213787a8 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:08:13 -0600 Subject: Cleaned up some 85xx PCI bugs * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming --- board/cds/mpc8548cds/init.S | 2 +- board/cds/mpc8548cds/mpc8548cds.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'board/cds/mpc8548cds') diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 34ca711..d468f5b 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -248,7 +248,7 @@ tlb1_entry: #define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) #define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff) +#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) #define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 0d3fceb..929ff2e 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -310,11 +310,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + mpc85xx_config_via_usbide, {0,0,0}}, {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {}, }; static struct pci_controller hose[] = { -- cgit v1.1