From f2cff6b104f82b993bef6086ce0c97159bbe1add Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:52 -0500 Subject: 8548cds PCIE support. Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/cds/mpc8548cds/mpc8548cds.c | 237 +++++++++++++++++++++++++++++++++----- 1 file changed, 205 insertions(+), 32 deletions(-) (limited to 'board/cds/mpc8548cds/mpc8548cds.c') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index b723641..242a68c 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt * @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -33,10 +34,15 @@ #include "../common/eeprom.h" #include "../common/via.h" +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif +DECLARE_GLOBAL_DATA_PTR; + extern long int spd_sdram(void); void local_bus_init(void); @@ -56,13 +62,6 @@ int checkboard (void) /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", @@ -71,20 +70,6 @@ int checkboard (void) printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - /* * Initialize local bus. */ @@ -102,6 +87,8 @@ int checkboard (void) */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; } @@ -176,6 +163,9 @@ local_bus_init(void) lbc->lcrr |= 0x00030000; asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ } /* @@ -301,7 +291,7 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -320,21 +310,175 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { {}, }; -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - +static struct pci_controller pci1_hose = { + config_table: pci_mpc85xxcds_config_table}; #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + void pci_init_board(void) { -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* outbound memory */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 2; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } #endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + } int last_stage_init(void) @@ -367,3 +511,32 @@ int last_stage_init(void) return 0; } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +} +#endif -- cgit v1.1 From 7f3f2bd2dc08e0b05e185662ca2e2d283757104a Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 27 Feb 2007 19:42:22 -0700 Subject: 85xxCDS: Add make targets for legacy systems. The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson --- board/cds/mpc8548cds/mpc8548cds.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'board/cds/mpc8548cds/mpc8548cds.c') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 242a68c..48753d7 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -299,14 +299,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; -- cgit v1.1