From 8907c2c50408b39e93fb42b2d74ab908480320a0 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 20 Aug 2013 11:44:43 -0700 Subject: i.MX6: nitrogen6x: force HDMI onto IPU0/DI0 Our Linux kernel switches the HDMI connector onto IPU0/DI1, but the U-Boot display driver only supports IPU0/DI0 for the time being. Because of this, a soft re-boot will leave the HDMI output connected to the wrong display port and prevent video from being displayed. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board/boundary/nitrogen6x') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 79ab449..1419f36 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -666,7 +666,8 @@ static void setup_display(void) writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <gpr[3]); -- cgit v1.1 From 67d54c39178aef2ea691c09dc115ed44ea92f46e Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 29 Aug 2013 12:37:36 -0700 Subject: i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor This clock isn't feeding anything under U-Boot, so there's no point in changing it from power-on default. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'board/boundary/nitrogen6x') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1419f36..f664f6d 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -622,7 +622,6 @@ int board_video_skip(void) static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; @@ -633,10 +632,6 @@ static void setup_display(void) reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &mxc_ccm->CCGR3); - /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); - writel(0x13<pfd_480_set); - /* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK -- cgit v1.1