From 761c70b80cdd3bead40146b96a8e713d6ae01632 Mon Sep 17 00:00:00 2001
From: Stelian Pop <stelian@popies.net>
Date: Thu, 8 May 2008 14:52:32 +0200
Subject: AT91SAM9RLEK: hook up the ATMEL LCD driver

This patch makes the necessary adaptations (PIO configurations and
defines in config header file) to hook up the Atmel LCD driver to the
AT91SAM9RLEK board.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 board/atmel/at91sam9rlek/at91sam9rlek.c | 63 +++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

(limited to 'board/atmel')

diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 8deecfd..10423d2 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -30,6 +30,8 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -124,6 +126,64 @@ static void at91sam9rlek_spi_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9RL_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
+	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
+	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
+	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
+	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
+	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
+	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
+
+	gd->fb_base = 0;
+}
+#endif
+
+
 int board_init(void)
 {
 	/* Enable Ctrlc */
@@ -141,6 +201,9 @@ int board_init(void)
 #ifdef CONFIG_HAS_DATAFLASH
 	at91sam9rlek_spi_hw_init();
 #endif
+#ifdef CONFIG_LCD
+	at91sam9rlek_lcd_hw_init();
+#endif
 	return 0;
 }
 
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