From ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 1 Mar 2007 21:11:36 +0100 Subject: [PATCH] Update AMCC Katmai 440SPe eval board support This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese --- board/amcc/katmai/katmai.c | 35 ++++++++++++++++++------- board/amcc/katmai/katmai.h | 65 ---------------------------------------------- 2 files changed, 25 insertions(+), 75 deletions(-) delete mode 100644 board/amcc/katmai/katmai.h (limited to 'board/amcc') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 8704925..fbf1a98 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -28,7 +28,6 @@ #include #include -#include "katmai.h" #include "../cpu/ppc4xx/440spe_pcie.h" #undef PCIE_ENDPOINT @@ -40,7 +39,6 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port); int board_early_init_f (void) { unsigned long mfr; - unsigned long pfc; /*----------------------------------------------------------------------+ * Interrupt controller setup for the Katmai 440SPe Evaluation board. @@ -228,15 +226,11 @@ int board_early_init_f (void) mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(sdr_mfr, mfr); */ - /* - * Setup GPIO signalling per defines in katmai.h - */ - pfc = PFC0_KATMAI; - mtsdr(SDR0_PFC0, pfc); + mtsdr(SDR0_PFC0, CFG_PFC0); - out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI); - out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI); - out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI); + out32(GPIO0_OR, CFG_GPIO_OR); + out32(GPIO0_ODR, CFG_GPIO_ODR); + out32(GPIO0_TCR, CFG_GPIO_TCR); return 0; } @@ -378,6 +372,23 @@ int is_pci_host(struct pci_controller *hose) return 1; } +int katmai_pcie_card_present(int port) +{ + u32 val; + + val = in32(GPIO0_IR); + switch (port) { + case 0: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0)); + case 1: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1)); + case 2: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2)); + default: + return 0; + } +} + static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; void pcie_setup_hoses(void) @@ -391,6 +402,10 @@ void pcie_setup_hoses(void) */ bus = 1; for (i = 0; i <= 2; i++) { + /* Check for katmai card presence */ + if (!katmai_pcie_card_present(i)) + continue; + #ifdef PCIE_ENDPOINT if (ppc440spe_init_pcie_endport(i)) { #else diff --git a/board/amcc/katmai/katmai.h b/board/amcc/katmai/katmai.h deleted file mode 100644 index 9d5b793..0000000 --- a/board/amcc/katmai/katmai.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __KATMAI_H_ -#define __KATMAI_H_ - -/*---------------------------------------------------------------------------- - * XX - * XXXX XX XXX XXX XXXX - * XX XX XX XX XX XX - * XX XXX XX XX XX XX XX - * XX XX XXXXX XX XX XX - * XXXX XX XXXX XXXX - * XXXX - * - * The 440SPe provices 32 bits of GPIO. By default all GPIO pins - * are disabled, and must be explicitly enabled by setting a - * bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the - * corresponding bit in the SDR0_PFC0 register (note that bit numbers - * reflect the PowerPC convention where bit 0 is the most-significant - * bit). - * - * Katmai specific: - * RS232_RX_EN# is held HIGH during reset by hardware, keeping the - * RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in - * Hi-Z condition. This prevents contention between the MAX3411 (U26) - * and 74CBTLV3125PG (U2) during reset. - * - * RS232_RX_EN# is connected as GPIO pin 30. Once the processor - * is released from reset, this pin must be configured as an output and - * then driven high to enable the receive signals from the UART transciever. - *----------------------------------------------------------------------------*/ -#define GPIO_ENABLE(gpio) (0x80000000 >> (gpio)) - -#define PFC0_KATMAI GPIO_ENABLE(30) -#define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */ -#define GPIO_TCR_KATMAI GPIO_ENABLE(30) -#define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */ - -#define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700) -#define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704) -#define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718) -#define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C) - -#endif /* __KATMAI_H_ */ -- cgit v1.1