From 2db64784061bfc34f4ba70ef1d2fbe7133b55670 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Mon, 1 Oct 2007 09:51:50 +0200 Subject: Program EPLD to force full duplex mode for PHY. EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki --- board/amcc/luan/luan.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7b16f8a..1bd7efa 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -66,8 +64,6 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ - return 0; } @@ -79,7 +75,18 @@ int board_early_init_f(void) int misc_init_r(void) { volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + /* set modes of operation */ + x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | + EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; + /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ + x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; + + /* put Ethernet+PHY in reset */ + x->ethuart &= ~EPLD2_RESET_ETH_N; + udelay(10000); + /* take Ethernet+PHY out of reset */ + x->ethuart |= EPLD2_RESET_ETH_N; return 0; } -- cgit v1.1 From 738815c0cc44aa329097f868dc1efc49ede9c5ba Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Oct 2007 11:44:46 +0200 Subject: ppc4xx: Coding style cleanup Signed-off-by: Stefan Roese --- board/amcc/luan/luan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/amcc') diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 1bd7efa..0067ce0 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -81,7 +81,7 @@ int misc_init_r(void) EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; - + /* put Ethernet+PHY in reset */ x->ethuart &= ~EPLD2_RESET_ETH_N; udelay(10000); -- cgit v1.1 From 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 15 Oct 2007 11:29:33 +0200 Subject: ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese --- board/amcc/sequoia/sequoia.c | 7 ++++--- board/amcc/yosemite/yosemite.c | 7 +++++-- 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index f823117..4e47ab3 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 @@ -24,6 +24,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -362,8 +363,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = in8(CFG_BCSR_BASE + 0); - val = in8(CFG_BCSR_BASE + 5) & 0x01; + rev = in_8((void *)(CFG_BCSR_BASE + 0)); + val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 912f09e..6ec922a 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -22,6 +24,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -181,8 +184,8 @@ int checkboard(void) printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); #endif - rev = *(u8 *)(CFG_CPLD + 0); - val = *(u8 *)(CFG_CPLD + 5) & 0x01; + rev = in_8((void *)(CFG_BCSR_BASE + 0)); + val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { -- cgit v1.1 From e2e93442e558cf1500e92861f99713b2f045ea22 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 15 Oct 2007 11:39:00 +0200 Subject: ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index f3803c0..e7997e9 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -25,6 +25,7 @@ #include #include #include +#include /* * There are 2 versions of production Sequoia & Rainier platforms. @@ -200,8 +201,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* check CPLD register +5 for PCI 66MHz flag */ - if (in8(CFG_BCSR_BASE + 5) & 0x01) - buf[5] += 0x10; + if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0) + /* + * PLB-to-PCI divisor = 3 for 33MHz sync PCI + * instead of 2 for 66MHz systems + */ + buf[5] |= 0x08; if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); -- cgit v1.1 From 3e11ae80fec1ee12194940955431186abf6009c2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 17 Oct 2007 15:40:19 +0200 Subject: ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'board/amcc') diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index e7997e9..6b9043a 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -40,7 +40,7 @@ * All Sequoias & Rainiers select from two possible EEPROMs in Boot * Config F. One for 33MHz PCI, one for 66MHz PCI. The following * values are for the 33MHz PCI configuration. Byte 5 (0 base) is - * the only value affected for a 66MHz PCI and simply needs a +0x10. + * the only value affected for a 33MHz PCI and simply needs a | 0x08. */ #define NAND_COMPATIBLE 0x01 @@ -57,6 +57,7 @@ static char *config_labels[] = { "CPU: 416 PLB: 166 OPB: 83 EBC: 55", "CPU: 500 PLB: 166 OPB: 83 EBC: 55", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 133 OPB: 66 EBC: 66", "CPU: 667 PLB: 166 OPB: 83 EBC: 55", NULL }; @@ -98,6 +99,11 @@ static u8 boot_configs[][17] = { 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, { + (NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { (NAND_COMPATIBLE | NOR_COMPATIBLE), 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 -- cgit v1.1