From 8a24c07ba5da2c72ad1f05e3eb8a463750200c98 Mon Sep 17 00:00:00 2001
From: Grant Erickson <gerickson@nuovations.com>
Date: Thu, 22 May 2008 14:44:24 -0700
Subject: ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling

This patch (Part 2 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/kilauea/init.S   | 227 +++++++++++++++++++++++---------------------
 board/amcc/kilauea/memory.c |   5 +
 board/amcc/makalu/Makefile  |   2 +-
 board/amcc/makalu/init.S    | 125 +-----------------------
 board/amcc/makalu/makalu.c  |   5 +
 board/amcc/makalu/memory.c  | 188 ------------------------------------
 6 files changed, 135 insertions(+), 417 deletions(-)
 delete mode 100644 board/amcc/makalu/memory.c

(limited to 'board/amcc')

diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
index 8cd534c..bf47d6b 100644
--- a/board/amcc/kilauea/init.S
+++ b/board/amcc/kilauea/init.S
@@ -1,8 +1,11 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * Based on code provided from UDTech and AMCC
+ * Originally based on code provided from UDTech and AMCC
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,125 +33,135 @@
 #include <ppc_defs.h>
 
 #define mtsdram_as(reg, value)		\
-	addi    r4,0,reg	;	\
-	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h	;	\
-	ori     r4,r4,value@l	;	\
-	mtdcr   memcfgd,r4	;
+	addi	r4,0,reg	;	\
+	mtdcr	memcfga,r4	;	\
+	addis	r4,0,value@h	;	\
+	ori	r4,r4,value@l	;	\
+	mtdcr	memcfgd,r4	;
+
+#if defined(CONFIG_DDR_ECC)
+	.extern ecc_init
+#endif /* defined(CONFIG_DDR_ECC) */
 
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
+#if !defined(CFG_INIT_DCACHE_CS)
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 
 	/*
-	 * DDR2 setup
+	 * DDR2 SDRAM Controller Setup
 	 */
 
-	/* Following the DDR Core Manual, here is the initialization */
-
-	/* Step 1 */
-
-	/* Step 2 */
-
-	/* Step 3 */
-
-	/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
-	mtsdram_as(SDRAM_MB0CF, 0x00006701);
-
-	/* SET SDRAM_MB1CF - Not enabled */
-	mtsdram_as(SDRAM_MB1CF, 0x00000000);
-
-	/* SET SDRAM_MB2CF  - Not enabled */
-	mtsdram_as(SDRAM_MB2CF, 0x00000000);
-
-	/* SET SDRAM_MB3CF  - Not enabled */
-	mtsdram_as(SDRAM_MB3CF, 0x00000000);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
-	mtsdram_as(SDRAM_CLKTR, 0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram_as(SDRAM_RTR, 0x06180000);
+	/* Set Memory Bank Configuration Registers */
+	mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
+	mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
+	mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
+	mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+
+	/* Set Memory Clock Timing Register */
+	mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+
+	/* Set Refresh Time Register */
+	mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
+
+	/* Set SDRAM Timing Registers */
+	mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
+	mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
+	mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+
+	/* Set Mode and Extended Mode Registers */
+	mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
+	mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+
+	/* Set Memory Controller Options 1 Register */
+	mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+
+	/* Set Manual Initialization Control Registers */
+	mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
+	mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
+	mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
+	mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
+	mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
+	mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
+	mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
+	mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
+	mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
+	mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
+	mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
+	mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
+	mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
+	mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
+	mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
+	mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+
+	/* Set On-Die Termination Registers */
+	mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
+	mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
+	mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+
+	/* Set Write Timing Register */
+	mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
 
-	/* SDRAM_SDTR1 */
-	mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram_as(SDRAM_SDTR2, 0x32204232);
+	/*
+	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
+	 * SDRAM0_MCOPT2[IPTR] = 1
+	 */
+	mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \
+				 SDRAM_MCOPT2_IPTR_EXECUTE);
 
-	/* SDRAM_SDTR3	*/
-	mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
+	/*
+	 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 *
+	 *   do {
+	 *           mfsdram(SDRAM_MCSTAT, val);
+	 *   } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
+	 */
+	li	r4,SDRAM_MCSTAT
+	lis	r2,SDRAM_MCSTAT_MIC_COMP@h
+	ori	r2,r2,SDRAM_MCSTAT_MIC_COMP@l
+0:	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
+	clrrwi	r3,r3,31
+	cmpw	cr7,r3,r2
+	bne+	cr7,0b
+
+	/* Set Delay Control Registers */
+	mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+	mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
+	mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
+	mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
 
-	mtsdram_as(SDRAM_MMODE, 0x00000442);
-	mtsdram_as(SDRAM_MEMODE, 0x00000404);
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 *
+	 *   mcopt2 = mfsdram(SDRAM_MCOPT2);
+	 */
+	li	r4,SDRAM_MCOPT2
+	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
 
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram_as(SDRAM_MCOPT1, 0x04322000);
+	/*
+	 *   mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
+	 */
+	mtdcr	memcfga,r4
+	oris	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h
+	ori	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l
+	mtdcr	memcfgd,r3
 
-	/* NOP */
-	mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 *   ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
 	 */
-	mtsdram_as(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
-	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
-	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
-	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
-	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram_as(SDRAM_CODT, 0x0080f837);
-	mtsdram_as(SDRAM_MODT0, 0x01800000);
-	mtsdram_as(SDRAM_MODT1, 0x00000000);
-
-	mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
-
-pll_wait:
-	bdnz	pll_wait
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram_as(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram_as(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram_as(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+	mflr	r13
+	lis	r3,CFG_SDRAM_BASE@h
+	ori	r3,r3,CFG_SDRAM_BASE@l
+	lis	r4,(CFG_MBYTES_SDRAM << 20)@h
+	ori	r4,r4,(CFG_MBYTES_SDRAM << 20)@l
+	bl	ecc_init
+	mtlr	r13
+#endif /* defined(CONFIG_DDR_ECC) */
+#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+#endif /* !defined(CFG_INIT_DCACHE_CS) */
 
 	blr
diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c
index 1d7a3fa..b7e2344 100644
--- a/board/amcc/kilauea/memory.c
+++ b/board/amcc/kilauea/memory.c
@@ -1,4 +1,7 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -30,10 +33,12 @@ void sdram_init(void)
 	return;
 }
 
+#if defined(CONFIG_NAND_U_BOOT)
 long int initdram(int board_type)
 {
 	return (CFG_MBYTES_SDRAM << 20);
 }
+#endif /* defined(CONFIG_NAND_U_BOOT) */
 
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
index 39328c2..4def0d4 100644
--- a/board/amcc/makalu/Makefile
+++ b/board/amcc/makalu/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_pll.o memory.o
+COBJS	= $(BOARD).o cmd_pll.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
index 11c5b19..4d0f460 100644
--- a/board/amcc/makalu/init.S
+++ b/board/amcc/makalu/init.S
@@ -1,8 +1,11 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * Based on code provided from Senao and AMCC
+ * Originally based on code provided from Senao and AMCC
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,126 +26,6 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#define mtsdram_as(reg, value)		\
-	addi    r4,0,reg	;	\
-	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h	;	\
-	ori     r4,r4,value@l	;	\
-	mtdcr   memcfgd,r4	;
-
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
-
-	/*
-	 * DDR2 setup
-	 */
-
-	/* Following the DDR Core Manual, here is the initialization */
-
-	/* Step 1 */
-
-	/* Step 2 */
-
-	/* Step 3 */
-
-	/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram_as(SDRAM_MB0CF, 0x00005201);
-
-	/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
-	mtsdram_as(SDRAM_CLKTR,0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram_as(SDRAM_RTR, 0x06180000);
-
-	/* SDRAM_SDTR1 */
-	mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram_as(SDRAM_SDTR2, 0x32204232);
-
-	/* SDRAM_SDTR3	*/
-	mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
-
-	mtsdram_as(SDRAM_MMODE, 0x00000442);
-	mtsdram_as(SDRAM_MEMODE, 0x00000404);
-
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram_as(SDRAM_MCOPT1, 0x04322000);
-
-	/* NOP */
-	mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
-	 */
-	mtsdram_as(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
-	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
-	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
-	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
-	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram_as(SDRAM_CODT, 0x0080f837);
-	mtsdram_as(SDRAM_MODT0, 0x01800000);
-#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
-	mtsdram_as(SDRAM_MODT1, 0x00000000);
-#endif
-
-	mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
-
-pll_wait:
-	bdnz	pll_wait
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram_as(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram_as(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram_as(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-
 	blr
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9baec9a..adf604f 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -351,3 +351,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 		       fdt_strerror(rc));
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+void sdram_init(void)
+{
+	return;
+}
diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c
deleted file mode 100644
index b03b60b..0000000
--- a/board/amcc/makalu/memory.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-void sdram_init(void)
-{
-	return;
-}
-
-long int initdram(int board_type)
-{
-	/*
-	 * Same as on Kilauea, Makalu generates exception 0x200
-	 * (machine check) after trap_init() in board_init_f,
-	 * when SDRAM is initialized here (late) and d-cache is
-	 * used earlier as INIT_RAM.
-	 * So for now, initialize DDR2 in init.S very early and
-	 * also use it for INIT_RAM. Then this exception doesn't
-	 * occur.
-	 */
-#if 0
-	u32 val;
-
-	/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
-	mtsdram(SDRAM_MB0CF, 0x00005201);
-
-	/* SET SDRAM_MB1CF - Not enabled */
-	mtsdram(SDRAM_MB1CF, 0x00000000);
-
-	/* SET SDRAM_MB2CF  - Not enabled */
-	mtsdram(SDRAM_MB2CF, 0x00000000);
-
-	/* SET SDRAM_MB3CF  - Not enabled */
-	mtsdram(SDRAM_MB3CF, 0x00000000);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
-	mtsdram(SDRAM_CLKTR, 0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram(SDRAM_RTR, 0x06180000);
-
-	/* SDRAM_SDTR1 */
-	mtsdram(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram(SDRAM_SDTR2, 0x32204232);
-
-	/* SDRAM_SDTR3	*/
-	mtsdram(SDRAM_SDTR3, 0x080b0d1a);
-
-	mtsdram(SDRAM_MMODE, 0x00000442);
-	mtsdram(SDRAM_MEMODE, 0x00000404);
-
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram(SDRAM_MCOPT1, 0x04322000);
-
-	/* NOP */
-	mtsdram(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
-	 */
-	mtsdram(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram(SDRAM_INITPLR11, 0x81000442);
-	mtsdram(SDRAM_INITPLR12, 0x81010780);
-	mtsdram(SDRAM_INITPLR13, 0x81010400);
-	mtsdram(SDRAM_INITPLR14, 0x00000000);
-	mtsdram(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram(SDRAM_CODT, 0x0080f837);
-	mtsdram(SDRAM_MODT0, 0x01800000);
-	mtsdram(SDRAM_MODT1, 0x00000000);
-
-	mtsdram(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	do {
-		mfsdram(SDRAM_MCSTAT, val);
-	} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mfsdram(SDRAM_MCOPT2, val);
-	val |= SDRAM_MCOPT2_DCEN_ENABLE;
-	mtsdram(SDRAM_MCOPT2, val);
-#endif
-	return (CFG_MBYTES_SDRAM << 20);
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-    printf ("testdram\n");
-#if defined (CONFIG_NAND_U_BOOT)
-    return 0;
-#endif
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x00001000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0xaaaaaaaa;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0x55555555;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-#if !defined (CONFIG_NAND_SPL)
-	printf ("SDRAM test passed!!!\n");
-#endif
-	return 0;
-}
-#endif
-- 
cgit v1.1


From ec724f883ee3f3925e6c55027e8ffa70ada83303 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 2 Jun 2008 17:13:55 +0200
Subject: ppc4xx: Change Kilauea to use the common DDR2 init function

This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/kilauea/Makefile |   3 +-
 board/amcc/kilauea/init.S   | 167 --------------------------------------------
 board/amcc/kilauea/memory.c |  84 ----------------------
 3 files changed, 1 insertion(+), 253 deletions(-)
 delete mode 100644 board/amcc/kilauea/init.S
 delete mode 100644 board/amcc/kilauea/memory.c

(limited to 'board/amcc')

diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
index 39328c2..981ef3a 100644
--- a/board/amcc/kilauea/Makefile
+++ b/board/amcc/kilauea/Makefile
@@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_pll.o memory.o
-SOBJS	= init.o
+COBJS	= $(BOARD).o cmd_pll.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
deleted file mode 100644
index bf47d6b..0000000
--- a/board/amcc/kilauea/init.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Originally based on code provided from UDTech and AMCC
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#define mtsdram_as(reg, value)		\
-	addi	r4,0,reg	;	\
-	mtdcr	memcfga,r4	;	\
-	addis	r4,0,value@h	;	\
-	ori	r4,r4,value@l	;	\
-	mtdcr	memcfgd,r4	;
-
-#if defined(CONFIG_DDR_ECC)
-	.extern ecc_init
-#endif /* defined(CONFIG_DDR_ECC) */
-
-	.globl  ext_bus_cntlr_init
-ext_bus_cntlr_init:
-#if !defined(CFG_INIT_DCACHE_CS)
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-
-	/*
-	 * DDR2 SDRAM Controller Setup
-	 */
-
-	/* Set Memory Bank Configuration Registers */
-	mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
-	mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
-	mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
-	mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
-
-	/* Set Memory Clock Timing Register */
-	mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
-
-	/* Set Refresh Time Register */
-	mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
-
-	/* Set SDRAM Timing Registers */
-	mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
-	mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
-	mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
-
-	/* Set Mode and Extended Mode Registers */
-	mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
-	mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
-
-	/* Set Memory Controller Options 1 Register */
-	mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
-
-	/* Set Manual Initialization Control Registers */
-	mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
-	mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
-	mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
-	mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
-	mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
-	mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
-	mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
-	mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
-	mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
-	mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
-	mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
-	mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
-	mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
-	mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
-	mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
-	mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
-
-	/* Set On-Die Termination Registers */
-	mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
-	mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
-	mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
-
-	/* Set Write Timing Register */
-	mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
-
-	/*
-	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
-	 * SDRAM0_MCOPT2[IPTR] = 1
-	 */
-	mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \
-				 SDRAM_MCOPT2_IPTR_EXECUTE);
-
-	/*
-	 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
-	 * completion of initialization.
-	 *
-	 *   do {
-	 *           mfsdram(SDRAM_MCSTAT, val);
-	 *   } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
-	 */
-	li	r4,SDRAM_MCSTAT
-	lis	r2,SDRAM_MCSTAT_MIC_COMP@h
-	ori	r2,r2,SDRAM_MCSTAT_MIC_COMP@l
-0:	mtdcr	memcfga,r4
-	mfdcr	r3,memcfgd
-	clrrwi	r3,r3,31
-	cmpw	cr7,r3,r2
-	bne+	cr7,0b
-
-	/* Set Delay Control Registers */
-	mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
-	mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
-	mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
-	mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
-
-	/*
-	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
-	 *
-	 *   mcopt2 = mfsdram(SDRAM_MCOPT2);
-	 */
-	li	r4,SDRAM_MCOPT2
-	mtdcr	memcfga,r4
-	mfdcr	r3,memcfgd
-
-	/*
-	 *   mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
-	 */
-	mtdcr	memcfga,r4
-	oris	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h
-	ori	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l
-	mtdcr	memcfgd,r3
-
-#if defined(CONFIG_DDR_ECC)
-	/*
-	 *   ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
-	 */
-	mflr	r13
-	lis	r3,CFG_SDRAM_BASE@h
-	ori	r3,r3,CFG_SDRAM_BASE@l
-	lis	r4,(CFG_MBYTES_SDRAM << 20)@h
-	ori	r4,r4,(CFG_MBYTES_SDRAM << 20)@l
-	bl	ecc_init
-	mtlr	r13
-#endif /* defined(CONFIG_DDR_ECC) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-#endif /* !defined(CFG_INIT_DCACHE_CS) */
-
-	blr
diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c
deleted file mode 100644
index b7e2344..0000000
--- a/board/amcc/kilauea/memory.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-
-void sdram_init(void)
-{
-	return;
-}
-
-#if defined(CONFIG_NAND_U_BOOT)
-long int initdram(int board_type)
-{
-	return (CFG_MBYTES_SDRAM << 20);
-}
-#endif /* defined(CONFIG_NAND_U_BOOT) */
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-    printf ("testdram\n");
-#if defined (CONFIG_NAND_U_BOOT)
-    return 0;
-#endif
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x00001000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0xaaaaaaaa;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++) {
-		*p = 0x55555555;
-	}
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-#if !defined (CONFIG_NAND_SPL)
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
-			return 1;
-		}
-	}
-#if !defined (CONFIG_NAND_SPL)
-	printf ("SDRAM test passed!!!\n");
-#endif
-	return 0;
-}
-#endif
-- 
cgit v1.1


From bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 2 Jun 2008 17:37:28 +0200
Subject: ppc4xx: Remove superfluous dram_init() call or replace it by
 initdram()

Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.

This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:

csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG

I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/acadia/memory.c     | 15 ------------
 board/amcc/bubinga/bubinga.c   | 16 -------------
 board/amcc/makalu/makalu.c     |  5 ----
 board/amcc/walnut/walnut.c     | 16 -------------
 board/amcc/yosemite/yosemite.c | 52 +++---------------------------------------
 5 files changed, 3 insertions(+), 101 deletions(-)

(limited to 'board/amcc')

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 709d41e..3dec315 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -33,14 +33,6 @@
 
 extern void board_pll_init_f(void);
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void cram_bcr_write(u32 wr_val)
 {
@@ -116,10 +108,3 @@ long int initdram(int board_type)
 
 	return (CFG_MBYTES_RAM << 20);
 }
-
-#ifndef CONFIG_NAND_SPL
-int testdram(void)
-{
-	return (0);
-}
-#endif
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index 66e7509..9d508b8 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -66,14 +66,6 @@ int checkboard(void)
 	return (0);
 }
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
 /* -------------------------------------------------------------------------
   initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
@@ -85,11 +77,3 @@ long int initdram(int board_type)
 	ret = spd_sdram();
 	return ret;
 }
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("test: xxx MB - ok\n");
-
-	return (0);
-}
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index adf604f..9baec9a 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -351,8 +351,3 @@ void ft_board_setup(void *blob, bd_t *bd)
 		       fdt_strerror(rc));
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-void sdram_init(void)
-{
-	return;
-}
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index 292e026..641987e 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -86,14 +86,6 @@ int checkboard(void)
 }
 
 /*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
-/*
  * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
@@ -101,11 +93,3 @@ long int initdram(int board_type)
 {
 	return spd_sdram();
 }
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("test: xxx MB - ok\n");
-
-	return (0);
-}
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 212fab8..8345537 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -200,7 +200,7 @@ int checkboard(void)
 }
 
 /*************************************************************************
- *  sdram_init -- doesn't use serial presence detect.
+ *  initdram -- doesn't use serial presence detect.
  *
  *  Assumes:    256 MB, ECC, non-registered
  *              PLB @ 133 MHz
@@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-void sdram_init(void)
+long int initdram(int board)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;
@@ -327,57 +327,11 @@ void sdram_init(void)
 
 	sdram_tr1_set(0x00000000, &tr1_bank1);
 	sdram_tr1_set(0x08000000, &tr1_bank2);
-	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
-}
+	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-/*************************************************************************
- *  long int initdram
- *
- ************************************************************************/
-long int initdram(int board)
-{
-	sdram_init();
 	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
-- 
cgit v1.1


From 3c1de1a6d36be9eee284a6c596a86e94f19cc5b2 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 19 May 2008 11:34:53 +0200
Subject: ppc4xx: Remove implementations of testdram()

This patch removes the used testdram() implementations of the board
that are maintained by myself.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/bamboo/bamboo.c           | 67 ------------------------------------
 board/amcc/canyonlands/canyonlands.c | 38 --------------------
 board/amcc/ebony/ebony.c             | 30 ----------------
 board/amcc/katmai/katmai.c           | 30 ----------------
 board/amcc/luan/luan.c               | 44 -----------------------
 board/amcc/ocotea/ocotea.c           | 30 ----------------
 board/amcc/sequoia/sequoia.c         | 38 --------------------
 board/amcc/taihu/taihu.c             | 42 ----------------------
 board/amcc/taishan/taishan.c         | 30 ----------------
 board/amcc/yucca/yucca.c             | 30 ----------------
 10 files changed, 379 deletions(-)

(limited to 'board/amcc')

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 5077187..0c7d69e 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -466,73 +466,6 @@ long int initdram (int board_type)
 #endif
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n, *p32, ctr;
-	const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
-
-	mtmsr(0);
-
-	for (k = 0; k <	CFG_MBYTES_SDRAM*1024;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-
-	/*
-	 * Perform a sequence test to ensure that all
-	 * memory locations are uniquely addressable
-	 */
-	ctr = 0;
-	p32 = 0;
-	while ((unsigned long)p32 != bend) {
-		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-			printf("Writing	%3d MB\r", (unsigned long)p32 >> 20);
-		*p32++ = ctr++;
-	}
-
-	ctr = 0;
-	p32 = 0;
-	while ((unsigned long)p32 != bend) {
-		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-			printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
-
-		if (*p32 != ctr) {
-			printf("SDRAM test fails at: %08x\n", p32);
-			return 1;
-		}
-
-		ctr++;
-		p32++;
-	}
-
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 0f66061..4e3b349 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -211,44 +211,6 @@ long int initdram(int board_type)
 }
 #endif
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 /*
  *  pci_target_init
  *
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index ededb3e..c6375ac 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -116,36 +116,6 @@ long int initdram(int board_type)
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 #if !defined(CONFIG_SPD_EEPROM)
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 193083f..3a0b18f 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) {
 	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index f964511..b14b6e1 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -126,50 +126,6 @@ u32 ddr_clktr(u32 default_val) {
 }
 
 /*************************************************************************
- *  int testdram()
- *
- ************************************************************************/
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *) 0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-
-	return  0;
-}
-#endif
-
-
-/*************************************************************************
  *  pci_pre_init
  *
  *  This routine is called just prior to registering the hose and gives
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 3bd1b81..79c1a1b 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -214,36 +214,6 @@ long int initdram (int board_type)
 }
 
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 #if !defined(CONFIG_SPD_EEPROM)
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 6bcb3ab..5ff9787 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -329,44 +329,6 @@ int checkboard(void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_MBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 /*
  * Assign interrupts to PCI devices.
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index eedde59..9bd30f9 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -196,45 +196,3 @@ int pci_pre_init(struct pci_controller *hose)
 	return 1;
 }
 #endif /* CONFIG_PCI */
-
-#ifdef CFG_DRAM_TEST
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-	unsigned long msr;
-	unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_EE));
-
-	for (k = 0; k < total_kbytes ;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0)
-			printf("%3d MB\r", k / 1024);
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	mtmsr(msr);
-
-	return 0;
-}
-#endif /* CFG_DRAM_TEST */
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index f00397e..b6c3065 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -196,36 +196,6 @@ int checkboard (void)
 	return (0);
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x04000000;
-	uint *pend = (uint *) 0x0fc00000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 11d1743..6608893 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) {
 	return default_val;
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) 0x00000000;
-	uint *pend = (uint *) 0x08000000;
-	uint *p;
-
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
-- 
cgit v1.1


From 72675dc6c06a48846d180106161d49dd714383cc Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 6 Jun 2008 15:55:21 +0200
Subject: ppc4xx: Unify AMCC's board config files (part 3/3)

This patch series unifies the AMCC eval board ports by introducing
a common include header for all AMCC eval boards:

include/configs/amcc-common.h

This header now includes all common configuration options/defines which
are removed from the board specific headers.

The reason for this is ease of maintenance and unified look and feel
of all AMCC boards.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/sequoia/config.mk | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'board/amcc')

diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
index e62b8d3..5e04ee4 100644
--- a/board/amcc/sequoia/config.mk
+++ b/board/amcc/sequoia/config.mk
@@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
 ifndef TEXT_BASE
 TEXT_BASE = 0xFFFA0000
+#
+# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000
+# TEXT_BASE = 0xFFF80000
+#
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
-- 
cgit v1.1