From 7f1913938984ef6c6a46cb53e003719196d9c5de Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:20:23 +0200 Subject: [PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki --- board/amcc/yucca/init.S | 12 ++++++------ board/amcc/yucca/yucca.c | 9 +++++---- 2 files changed, 11 insertions(+), 10 deletions(-) (limited to 'board/amcc/yucca') diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index c92dcf7..67e8f8f 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -70,9 +70,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -112,9 +112,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d08fcf3..252e4fe 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -855,7 +855,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) @@ -874,8 +874,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -899,6 +899,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } -- cgit v1.1 From 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:35:37 +0200 Subject: [PPC440SPe] PCIe environment settings for Katmai and Yucca - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki --- board/amcc/yucca/yucca.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'board/amcc/yucca') diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 252e4fe..397b018 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ -- cgit v1.1